Blaise Tine
|
5419859281
|
fcvt fix
|
2021-01-25 02:22:00 -08:00 |
|
Blaise Tine
|
7ae936c25f
|
minor updates
|
2021-01-14 23:06:03 -08:00 |
|
Blaise Tine
|
fe64c47f60
|
ccip write fix
|
2021-01-14 22:49:06 -08:00 |
|
Blaise Tine
|
f18ac24675
|
afu reset fix
|
2021-01-12 17:13:47 -08:00 |
|
Blaise Tine
|
b4b5d6f0ab
|
minor updates
|
2021-01-12 15:19:38 -08:00 |
|
Blaise Tine
|
7c4823e65c
|
fixed GPR reset bug, fixed lsu dup loading, fixed riscv-tests
|
2021-01-11 23:55:09 -08:00 |
|
Blaise Tine
|
5c83c594c1
|
minor update
|
2021-01-07 17:25:59 -08:00 |
|
Blaise Tine
|
146c285aa0
|
minor update
|
2021-01-06 19:59:04 -08:00 |
|
Blaise Tine
|
2b8435471a
|
speeding up simulation using dedicated full dpi-based FPU core
|
2021-01-06 18:44:06 -08:00 |
|
Blaise Tine
|
39bff921be
|
cache bug fixes
|
2021-01-05 05:04:49 -08:00 |
|
Blaise Tine
|
762b8e2e3e
|
fixed cache mshr critical path
|
2021-01-04 12:49:40 -05:00 |
|
Blaise Tine
|
4bc3b537bd
|
fixed reset fan-out
|
2021-01-03 20:06:36 -08:00 |
|
Blaise Tine
|
4815ab099c
|
using single-port block ram for cache tags, restoring core reset signal
|
2021-01-02 19:53:41 -08:00 |
|
Blaise Tine
|
30d950ada2
|
vx_spawn_warps redesign using opencl's style scheduler
|
2021-01-01 14:13:48 -05:00 |
|
Blaise Tine
|
138db29310
|
Merge branch 'master' of https://github.gatech.edu/casl/Vortex
|
2020-12-31 22:40:34 -05:00 |
|
Blaise Tine
|
e4a00dd0d9
|
fixed loader script stack setup
|
2020-12-31 22:37:20 -05:00 |
|
Blaise Tine
|
abe32ed553
|
cache optimization - moved read requests to stage1 and eliminating stage3
|
2020-12-31 07:40:58 -08:00 |
|
Blaise Tine
|
d44144f72f
|
FPU float<->int conversion optimization
|
2020-12-29 15:37:45 -08:00 |
|
Blaise Tine
|
4f689c4ce9
|
fixed global obejct sharing between cores
|
2020-12-24 19:36:07 -05:00 |
|
Blaise Tine
|
703a861fe9
|
added support for write-through cache, removed cache snooping support
|
2020-12-23 23:51:02 -08:00 |
|
Blaise Tine
|
d956e268b9
|
adding new performance counters (banks utilization and DRAM bus utilization)
|
2020-12-22 12:33:45 -08:00 |
|
Blaise Tine
|
4bbd7bf408
|
performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,
|
2020-12-19 02:45:06 -08:00 |
|
Blaise Tine
|
29cd2f5dff
|
fixed register file initialization to zero synthesis inference
|
2020-12-10 00:27:56 -08:00 |
|
Blaise Tine
|
707ba3760f
|
minor update
|
2020-12-08 21:37:53 -08:00 |
|
Blaise Tine
|
d5438fd591
|
merging perf counters
|
2020-12-08 21:02:39 -08:00 |
|
Blaise Tine
|
14baec86d5
|
moved apae sources into rtl/afu
|
2020-12-08 04:59:11 -08:00 |
|
Blaise Tine
|
d5fa82f5e4
|
cache req datapath optimizations
|
2020-12-08 02:58:08 -08:00 |
|
Xandy Liu
|
1595ff08e2
|
PERF pipeline stalls and cache
|
2020-12-08 01:14:41 -05:00 |
|
Blaise Tine
|
d68b32cd60
|
minor update
|
2020-12-06 22:40:27 -08:00 |
|
Blaise Tine
|
b7a724410b
|
update DRAM simulation - reduce the latency of duplicate requests (simulate DRAM cache)
|
2020-12-03 07:30:19 -08:00 |
|
Blaise Tine
|
b85391389b
|
rename MSRQ to MSHR
|
2020-11-28 17:32:00 -05:00 |
|
Blaise Tine
|
00d7473268
|
build warnings clean
|
2020-11-28 14:59:13 -05:00 |
|
Blaise Tine
|
461be0880d
|
fixed FPU-CSR data dependence
|
2020-11-25 09:05:38 -08:00 |
|
Blaise Tine
|
c04d385641
|
minor update
|
2020-11-23 20:12:04 -08:00 |
|
Blaise Tine
|
664ce28426
|
minor update
|
2020-11-23 12:21:39 -08:00 |
|
Blaise Tine
|
2d4fef6dd6
|
fixed fp_noncomp bug, ci toolchain script update, increased DRAM latency to 100 cycles
|
2020-11-23 11:59:40 -08:00 |
|
Blaise Tine
|
20f22c7446
|
scope minor fix
|
2020-11-22 11:51:46 -08:00 |
|
Blaise Tine
|
1795980a52
|
L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization
|
2020-11-21 09:47:56 -08:00 |
|
Blaise Tine
|
34b650be94
|
fixed shared memory addressing critical path, fixed VX_fp_noncomp output bug
|
2020-11-17 00:27:24 -08:00 |
|
Blaise Tine
|
61add25d96
|
minor fix
|
2020-11-16 08:23:16 -08:00 |
|
Blaise Tine
|
77bca2deca
|
constant integration updates
|
2020-11-16 02:39:53 -08:00 |
|
Blaise Tine
|
e946d976e7
|
constant integration updates
|
2020-11-15 08:44:57 -08:00 |
|
Blaise Tine
|
5d58bf3d11
|
fixed l3cache hang using memory arbiter in afu
|
2020-11-15 06:36:32 -08:00 |
|
Blaise Tine
|
2e0f51af80
|
fixed instr/cycle perf counter
|
2020-11-12 11:41:25 -08:00 |
|
Blaise Tine
|
ce95c40aee
|
fixed redundant cache fills
|
2020-11-11 12:07:27 -05:00 |
|
Blaise Tine
|
0bacfd2dae
|
minor update
|
2020-11-10 13:47:28 -05:00 |
|
Blaise Tine
|
725322807e
|
fixed DRAM response backpressure inside Cache
|
2020-11-10 05:24:57 -08:00 |
|
Blaise Tine
|
ed69be4027
|
pipeline optimization: fixed GPR fanout delay to execute unitsddddssssvcd
|
2020-11-09 21:41:06 -08:00 |
|
Blaise Tine
|
7c384eaf7f
|
fixed snoop forwarding hang
|
2020-11-09 20:02:33 -08:00 |
|
Blaise Tine
|
f8d54c6994
|
fixed cache_core_rsp_merge unit
|
2020-11-09 02:10:35 -08:00 |
|