minor update

driver/opae/Makefile

@@ -36,6 +36,10 @@ ASE_DIR = ase
 
 VLSIM_DIR = vlsim
 
+RTL_DIR=../../hw/rtl
+
+SCRIPT_DIR=../../hw/scripts
+
 PROJECT = libvortex.so
 
 PROJECT_ASE = $(ASE_DIR)/libvortex.so
@@ -50,7 +54,8 @@ SRCS = vortex.cpp ../common/vx_utils.cpp
 ifdef SCOPE
 	CXXFLAGS += -DSCOPE	
 	SRCS += vx_scope.cpp
-	SET_SCOPE = SCOPE=1
+	SCOPE_ENABLE = SCOPE=1
+	SCOPE_H = scope-defs.h 
 endif
 
 all: vlsim
@@ -59,7 +64,16 @@ all: vlsim
 json: ../../hw/opae/vortex_afu.json
 	afu_json_mgr json-info --afu-json=$^ --c-hdr=$@
 
-fpga: $(SRCS)
+scope-defs.h: $(SCRIPT_DIR)/scope.json
+	$(SCRIPT_DIR)/scope.py $(RTL_INCLUDE) $(CONFIGS) -cc scope-defs.h -vl $(RTL_DIR)/scope-defs.vh $(SCRIPT_DIR)/scope.json
+
+# generate scope data
+scope: scope-defs.h
+
+vlsim-hw: $(SCOPE_H)
+	$(SCOPE_ENABLE) $(MAKE) -C vlsim
+
+fpga: $(SRCS) $(SCOPE_H)
 	$(CXX) $(CXXFLAGS) -DUSE_FPGA $^ $(LDFLAGS) $(FPGA_LIBS) -o $(PROJECT)
 
 asesim: $(SRCS) $(ASE_DIR)
@@ -68,9 +82,6 @@ asesim: $(SRCS) $(ASE_DIR)
 vlsim: $(SRCS) vlsim-hw
 	$(CXX) $(CXXFLAGS) -DUSE_VLSIM $(SRCS) $(LDFLAGS) -L./vlsim $(VLSIM_LIBS) -o $(PROJECT_VLSIM)
 
-vlsim-hw:
-	$(SET_SCOPE) $(MAKE) -C vlsim
-
 vortex.o: vortex.cpp
 	$(CXX) $(CXXFLAGS) -c vortex.cpp -o $@
 

driver/opae/vlsim/Makefile

@@ -40,8 +40,6 @@ TOP = vortex_afu_shim
 
 RTL_DIR=../../../hw/rtl
 
-SCRIPT_DIR=../../../hw/scripts
-
 SRCS = fpga.cpp opae_sim.cpp
 SRCS += $(RTL_DIR)/fp_cores/svdpi/float_dpi.cpp
 
@@ -70,7 +68,6 @@ endif
 ifdef SCOPE
 	VL_FLAGS += -DSCOPE
 	CFLAGS += -DSCOPE
-	SCOPE_VH = $(RTL_DIR)/scope-defs.vh 
 endif
 
 # use our OPAE shim
@@ -85,14 +82,8 @@ RTL_INCLUDE += -I../../../hw/opae  -I../../../hw/opae/ccip
 PROJECT = libopae-c-vlsim.so
 
 all: $(PROJECT)
-
-# generate scope data
-scope: $(RTL_DIR)/scope-defs.vh
-
-$(RTL_DIR)/scope-defs.vh: $(SCRIPT_DIR)/scope.json
-	$(SCRIPT_DIR)/scope.py $(RTL_INCLUDE) $(CONFIGS) -cc ../scope-defs.h -vl $(RTL_DIR)/scope-defs.vh $(SCRIPT_DIR)/scope.json
 	
-$(PROJECT): $(SRCS) $(SCOPE_VH)
+$(PROJECT): $(SRCS)
 	verilator --exe --cc $(TOP) --top-module $(TOP) $(RTL_INCLUDE) $(VL_FLAGS) $(SRCS) -CFLAGS '$(CFLAGS)' -LDFLAGS '$(LDFLAGS)' -o ../$(PROJECT)
 	make -j -C obj_dir -f V$(TOP).mk
 

driver/opae/vx_scope.cpp

@@ -57,7 +57,7 @@ static std::thread g_timeout_thread;
 static std::mutex g_timeout_mutex;
 
 static void timeout_callback(fpga_handle fpga) {
-    std::this_thread::sleep_for(std::chrono::seconds{60});
+    std::this_thread::sleep_for(std::chrono::seconds{HANG_TIMEOUT});
     vx_scope_stop(fpga, HANG_TIMEOUT);
     fpgaClose(fpga);
     exit(0);
@@ -109,7 +109,7 @@ int vx_scope_start(fpga_handle hfpga, uint64_t delay) {
         // set start delay
         uint64_t cmd_delay = ((delay << 3) | CMD_SET_DELAY);
         CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, cmd_delay));    
-        std::cout << "scope start delay: " << delay << std::endl;
+        std::cout << "scope start delay: " << std::dec << delay << "s" << std::endl;
     }
 
 #ifdef HANG_TIMEOUT
@@ -133,9 +133,11 @@ int vx_scope_stop(fpga_handle hfpga, uint64_t delay) {
         // stop recording
         uint64_t cmd_stop = ((delay << 3) | CMD_SET_STOP);
         CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, cmd_stop));
-        std::cout << "scope stop delay: " << delay << std::endl;
+        std::cout << "scope stop delay: " << std::dec << delay << "s" << std::endl;
     }
 
+    std::cout << "scope trace dump begin..." << std::endl;
+
     std::ofstream ofs("vx_scope.vcd");
 
     ofs << "$version Generated by Vortex Scope $end" << std::endl;
@@ -146,6 +148,8 @@ int vx_scope_stop(fpga_handle hfpga, uint64_t delay) {
     dump_taps(ofs, -1);
     ofs << "$upscope $end" << std::endl;
     ofs << "enddefinitions $end" << std::endl;
+
+    std::cout << "OK" << std::flush << std::endl;
     
     uint64_t frame_width, max_frames, data_valid, offset, delta;   
     uint64_t timestamp = 0;
@@ -163,7 +167,7 @@ int vx_scope_stop(fpga_handle hfpga, uint64_t delay) {
         std::this_thread::sleep_for(std::chrono::seconds(1));
     } while (true);
 
-    std::cout << "scope trace dump begin..." << std::endl;    
+    std::cout << "OK" << std::flush << std::endl;
 
     // get frame width
     CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, CMD_GET_WIDTH));
@@ -235,7 +239,7 @@ int vx_scope_stop(fpga_handle hfpga, uint64_t delay) {
                     signal_id = num_taps;
                     if (0 == (frame_no % FRAME_FLUSH_SIZE)) {
                         ofs << std::flush;
-                        std::cout << "*** " << frame_no << " frames, timestamp=" << timestamp << std::endl;
+                        std::cout << "*** " << frame_no << " frames, timestamp=" << timestamp << std::flush << std::endl;
                     }
                 }                     
             }