felsabbagh3
|
797801ebae
|
CENA/CENB Modifications + Still not working
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2019-10-19 14:52:57 -04:00 |
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felsabbagh3
|
4cae140ac1
|
Mem technology compiling but still reading all zeros
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2019-10-18 16:45:42 -04:00 |
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felsabbagh3
|
f7d826593f
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TMC working and tested
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2019-10-18 16:09:06 -04:00 |
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felsabbagh3
|
f7b55427b4
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Added ISA2 infrastructure with bugs
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2019-10-18 05:21:32 -04:00 |
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felsabbagh3
|
629ed3f8f9
|
Before ISA2.0
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2019-10-18 04:15:34 -04:00 |
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felsabbagh3
|
559c64cb36
|
Cleanup
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2019-10-18 02:20:38 -04:00 |
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felsabbagh3
|
505bbc20c8
|
Removed FWD
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2019-10-18 02:01:39 -04:00 |
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felsabbagh3
|
6b729fd2ea
|
minor
|
2019-10-18 01:46:38 -04:00 |
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felsabbagh3
|
ccbb2acab5
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LSU+EXU minor
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2019-10-17 22:38:09 -04:00 |
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felsabbagh3
|
6779d0fade
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Instruction Multiplex LSU/EXU 1 cycle DONE
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2019-10-17 22:29:21 -04:00 |
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Lingjun Zhu
|
a4d6ada16d
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Fixed the issues of memory during synthesis
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2019-10-17 14:18:52 -04:00 |
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felsabbagh3
|
9bf186fc77
|
minor
|
2019-10-17 11:51:11 -04:00 |
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felsabbagh3
|
e8a43fa7a9
|
minor
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2019-10-17 11:44:19 -04:00 |
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felsabbagh3
|
10fbb53c38
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minor
|
2019-10-17 11:29:40 -04:00 |
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felsabbagh3
|
33e20a2d80
|
minor
|
2019-10-17 11:25:29 -04:00 |
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felsabbagh3
|
b08297eafb
|
minor
|
2019-10-17 11:04:06 -04:00 |
|
felsabbagh3
|
7fd5312b67
|
minor
|
2019-10-17 10:50:36 -04:00 |
|
felsabbagh3
|
95047fcadc
|
Rename Stage that removes the need for forwarding
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2019-10-17 00:48:54 -04:00 |
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felsabbagh3
|
8bc3b8b0a5
|
Need to link SystemC for sc_time_stamp()
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2019-10-14 23:25:14 -04:00 |
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felsabbagh3
|
22f02820cf
|
GPR back-end with mem
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2019-10-14 19:10:47 -04:00 |
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felsabbagh3
|
ee83e6d8c8
|
Moved GPR to back-end
|
2019-10-14 19:08:32 -04:00 |
|
Lingjun Zhu
|
f28cd286e6
|
Implemented the GPR model with the CLN28HPC memory block
|
2019-10-13 20:27:28 -04:00 |
|
Lingjun Zhu
|
d5dad1c442
|
Updated the two-port GPR model
|
2019-10-13 19:52:14 -04:00 |
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felsabbagh3
|
e67310acfb
|
New Warp Scheduler + VCD Enable
|
2019-09-15 00:12:41 -04:00 |
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felsabbagh3
|
fb3bc60189
|
Finalized GPR with 3-Port Structure
|
2019-09-11 14:53:32 -04:00 |
|
felsabbagh3
|
1b25b10644
|
Full Evaluation Attempt 1
|
2019-09-11 01:39:00 -04:00 |
|
felsabbagh3
|
3c3a443bd5
|
New RF with Evaluation
|
2019-09-11 01:04:23 -04:00 |
|
felsabbagh3
|
8d143d7739
|
Quartus + GPR evaluation
|
2019-09-10 20:23:01 -04:00 |
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felsabbagh3
|
4e8da1811a
|
New GPR structure - Clone or WSPAWN
|
2019-09-09 22:17:20 -04:00 |
|
felsabbagh3
|
1882147370
|
GPR Wrapper Interface Done
|
2019-09-09 14:04:07 -04:00 |
|
felsabbagh3
|
bce9bc443c
|
GPR Wrapper in Decode
|
2019-09-09 01:03:13 -04:00 |
|
felsabbagh3
|
ecf81336db
|
Finished FE and BE high-level
|
2019-09-08 19:28:53 -04:00 |
|
felsabbagh3
|
981bf0afe5
|
FE Done
|
2019-09-08 18:36:47 -04:00 |
|
felsabbagh3
|
ad45758a35
|
Before Fetch->FE
|
2019-09-08 18:09:11 -04:00 |
|
felsabbagh3
|
c310e7381f
|
Icache interface
|
2019-09-08 17:36:09 -04:00 |
|
felsabbagh3
|
5e6804703f
|
Decode in FE
|
2019-09-08 17:24:51 -04:00 |
|
felsabbagh3
|
ac9b06bf7d
|
Before FE BE abstraction
|
2019-09-08 16:21:37 -04:00 |
|
felsabbagh3
|
fe09aafbb4
|
Interface Checkpoint 2 - Remove Lints
|
2019-09-05 19:32:37 -04:00 |
|
felsabbagh3
|
2d0e41db63
|
checkpoint: Added icache struct
|
2019-09-03 16:19:06 -04:00 |
|
Hyesoon Kim
|
6b3b124a30
|
fix typo of std=c++11
|
2019-06-12 07:32:20 -04:00 |
|
felsabbagh3
|
9cd8ee8579
|
Added std=c++11
|
2019-06-11 23:21:48 -07:00 |
|
felsabbagh3
|
1105261bbb
|
Updated Quartus paths
|
2019-06-11 21:16:50 -07:00 |
|
felsabbagh3
|
b216da5a6a
|
ram stdint + Quartus Files
|
2019-06-11 21:13:30 -07:00 |
|
felsabbagh3
|
d7afef04a9
|
Sim Work miss
|
2019-05-18 23:42:55 +04:00 |
|
felsabbagh3
|
8995267cd3
|
Added barriers
|
2019-05-17 08:34:00 +04:00 |
|
felsabbagh3
|
48468ed26a
|
Proper SIMT with fine-grain scheduler implemented
|
2019-05-10 00:49:54 -07:00 |
|
felsabbagh3
|
96dac5e1ce
|
Warp + Context Aware Design - Global Stalling
|
2019-05-08 16:32:49 -07:00 |
|
felsabbagh3
|
a6c13bc38c
|
Inefficient context aware desgin
|
2019-05-08 15:55:06 -07:00 |
|
felsabbagh3
|
79356c7ab1
|
Changed hierarchy + Identified private + public modules
|
2019-05-07 23:45:05 -07:00 |
|
felsabbagh3
|
191ed73415
|
Less expensive but slower fetch logic
|
2019-05-05 22:55:47 -04:00 |
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