Blaise Tine
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3f5fa64085
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Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
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2020-05-21 00:00:29 -07:00 |
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Blaise Tine
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f14996b4ae
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minor update
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2020-05-20 23:54:27 -07:00 |
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felsabbagh3
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7e091b53f8
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Added valid_table in scheduler and removed rename_table on reset
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2020-05-20 23:02:41 -07:00 |
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Blaise Tine
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a8bf62a168
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minor update
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2020-05-20 21:05:29 -04:00 |
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Blaise Tine
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240bdae13d
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minor update
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2020-05-20 20:58:17 -04:00 |
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Blaise Tine
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1102871180
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force random values for unitialized signals
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2020-05-20 20:57:15 -04:00 |
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Blaise Tine
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7e5fed3ec1
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Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
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2020-05-20 18:27:20 -04:00 |
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Blaise Tine
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d4cb8b6f66
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fixed renaem table reset logic
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2020-05-20 18:24:09 -04:00 |
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Blaise Tine
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72d54c749c
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fixed cache msrq reset logic
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2020-05-20 18:11:31 -04:00 |
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Blaise Tine
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e1b4862f85
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minor update
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2020-05-20 14:14:29 -07:00 |
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Blaise Tine
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cefd0d85af
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rtl refactoring
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2020-05-20 16:59:14 -04:00 |
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Blaise Tine
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b5569dd525
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OPAE rtl fixes
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2020-05-20 12:08:10 -07:00 |
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Blaise Tine
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e3bead147a
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erge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
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2020-05-19 17:40:45 -07:00 |
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Blaise Tine
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c37e6e2207
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opae rtl fixes
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2020-05-19 17:36:18 -07:00 |
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felsabbagh3
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cad92bbeb1
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Qualify scheduler_delay with valid signal
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2020-05-19 14:59:17 -07:00 |
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Blaise Tine
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c209d902a3
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update
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2020-05-19 17:41:51 -04:00 |
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Blaise Tine
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e269909db9
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opae rtl fixes
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2020-05-19 13:47:47 -07:00 |
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Blaise Tine
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0c88da2bfb
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opae rtl fixes
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2020-05-18 20:19:02 -07:00 |
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Blaise Tine
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11ace25f27
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opae rtl fixes
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2020-05-17 20:29:42 -07:00 |
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felsabbagh3
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26f9fc96c3
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Corner case where the pipeline is stalled, makes mrvq entereis valid, but when unstalled mrvq_init isn't set up correctly
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2020-05-16 21:20:57 -07:00 |
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felsabbagh3
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101de6b138
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mrvq update ready + init ready as 1 in same cycle causing incorrect ready state
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2020-05-16 18:52:30 -07:00 |
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felsabbagh3
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794664363c
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Commented rtlsim dynamiclib for mac
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2020-05-16 18:02:37 -07:00 |
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felsabbagh3
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f55a1be6cb
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Commented mac dynamiclib in basic
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2020-05-16 18:01:20 -07:00 |
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felsabbagh3
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4bf0bcca8a
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Fix incorrect CSR forwarding for GID between different warps
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2020-05-16 17:56:15 -07:00 |
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felsabbagh3
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e2741f9cdb
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Force miss_add init ready to 1 when core req matches with mrvq entry, regardless of hit/miss
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2020-05-16 16:26:26 -07:00 |
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Blaise Tine
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544f272ff9
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update
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2020-05-16 18:16:14 -04:00 |
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Blaise Tine
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d6c87dbb0a
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added debug print states or rtl
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2020-05-16 14:19:17 -04:00 |
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Blaise Tine
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65c2da76cf
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snooping response handling fix
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2020-05-14 23:34:52 -04:00 |
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Blaise Tine
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57a037b2f4
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snooping response handling fix
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2020-05-14 23:06:15 -04:00 |
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Blaise Tine
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d623ef4029
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snooping response handling fix
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2020-05-14 23:05:46 -04:00 |
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Blaise Tine
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bcb9514799
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snooping response handling fix
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2020-05-14 11:01:41 -04:00 |
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felsabbagh3
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ff140b6811
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Added an initial ready state to an mrvq entry that might be set to 1
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2020-05-12 21:47:51 -07:00 |
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felsabbagh3
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5b2624046e
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Avoid snoop deadlock whith snoops. Adds mrvq not almost full for snrq pop
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2020-05-12 21:30:17 -07:00 |
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felsabbagh3
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b08b80156d
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Added pending request check. This applies when 1) mrvq entery is valid/ready but not head, then a core request hits 2) snoop when pending write. A pending miss request is either a valid entry in mrvq OR a miss entery in st2
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2020-05-12 21:25:13 -07:00 |
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Blaise Tine
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b0b38f6c24
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snooping response handling fix
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2020-05-12 18:52:24 -04:00 |
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Blaise Tine
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1eda9b34d5
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snooping response handling fix
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2020-05-12 13:36:55 -04:00 |
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Blaise Tine
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fcf3800d5d
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snooping response handling fix
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2020-05-12 13:35:18 -04:00 |
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Blaise Tine
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c49f01b769
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snooping response handling
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2020-05-11 22:55:44 -04:00 |
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Blaise Tine
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b6c4aa0baa
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rtl refactoring
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2020-05-10 09:52:38 -04:00 |
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Blaise Tine
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cc84e0691c
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multicore fix
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2020-05-10 08:30:04 -04:00 |
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Blaise Tine
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359601cfd3
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OPAE rtl fixes
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2020-05-08 13:16:44 -07:00 |
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Blaise Tine
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c2e9240b7d
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OPAE rtl fixes
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2020-05-08 08:28:28 -07:00 |
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Blaise Tine
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13dfd5c8c7
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rtl multicore fix
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2020-05-07 02:20:12 -04:00 |
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Blaise Tine
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de9fc68ccc
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opae fixes
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2020-05-06 21:14:53 -07:00 |
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Blaise Tine
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59cc0d5be9
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rtl multicore fix
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2020-05-06 13:33:16 -04:00 |
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Blaise Tine
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330bbc4f56
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rtl gpr multicore fix
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2020-05-06 09:05:10 -04:00 |
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Blaise Tine
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b1fdf0a947
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fix rtl gpr zero
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2020-05-06 05:25:20 -04:00 |
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Blaise Tine
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7e748e4e38
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rtl refactoring
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2020-05-05 16:28:14 -04:00 |
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Blaise Tine
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5def6d0da6
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rtl refactoring
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2020-05-05 13:32:50 -04:00 |
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Blaise Tine
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2ab90e9436
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rtl refactoring
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2020-05-05 13:31:50 -04:00 |
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