felsabbagh3
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9b989cec69
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Fixed use before init
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2020-04-04 18:41:25 -07:00 |
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felsabbagh3
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165836332c
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Fixed snp delay for sm
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2020-04-04 18:21:25 -07:00 |
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felsabbagh3
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bcea9866a7
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Fixed a couple of things
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2020-04-04 18:20:06 -07:00 |
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felsabbagh3
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d0765b8fb1
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Now Flush Routine only sends one round of snoops
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2020-04-04 18:02:57 -07:00 |
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felsabbagh3
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65fa9285bf
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Fixed Flushing and Prefetching
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2020-04-04 17:57:35 -07:00 |
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felsabbagh3
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a7a1906bea
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Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
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2020-04-04 10:14:24 -07:00 |
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felsabbagh3
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70bd673031
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Resseting GPR
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2020-04-04 10:13:26 -07:00 |
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Blaise Tine
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07ec0ef344
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OPAE hw snooping fixes
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2020-04-04 05:07:45 -07:00 |
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Blaise Tine
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1f63139ce5
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fix RTL code undefined variables
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2020-04-03 22:59:40 -07:00 |
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felsabbagh3
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10e445d459
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Provisioned Prefetching, currently disabled
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2020-04-03 00:30:33 -07:00 |
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felsabbagh3
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7d1cc5234e
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Fixed dram_fill_accept dependant on input address
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2020-04-02 20:26:37 -07:00 |
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felsabbagh3
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0e0b326b31
|
Removed bank Hazard Signals
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2020-04-02 19:19:00 -07:00 |
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felsabbagh3
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7b4b44e5ab
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Fixed DRAM random latency simulator
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2020-03-31 20:33:45 -07:00 |
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felsabbagh3
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1b9d9f3625
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Fixed incorrect miss_add on pipeline stall
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2020-03-31 20:23:09 -07:00 |
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Blaise Tine
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bca5ac5e7f
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enable rtl sim dram stalls
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2020-03-31 02:41:14 -04:00 |
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Blaise Tine
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e92c4b6774
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enable rtl sim dram stalls
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2020-03-31 02:38:18 -04:00 |
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felsabbagh3
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bcf894b581
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Demo SOC W=8, T=4 Passing
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2020-03-30 22:17:38 -07:00 |
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felsabbagh3
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66a837b0df
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SOC only 2 errors
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2020-03-30 21:28:40 -07:00 |
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felsabbagh3
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88f2ad53d0
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Fixed simulator includes
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2020-03-30 16:43:26 -07:00 |
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Blaise Tine
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f6eb5dfbae
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refactor RTL sim, added DRAM stalls support
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2020-03-30 04:13:19 -04:00 |
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felsabbagh3
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638625184f
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Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
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2020-03-29 23:46:44 -07:00 |
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felsabbagh3
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ff2b8dba12
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Fixed req_addr width
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2020-03-29 23:46:38 -07:00 |
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Blaise Tine
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0f39d0fcbd
|
Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
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2020-03-30 01:53:53 -04:00 |
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Blaise Tine
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2eb19e23c2
|
refactor RTL simulator
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2020-03-30 01:53:34 -04:00 |
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felsabbagh3
|
ccc65a06fe
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Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
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2020-03-29 21:22:08 -07:00 |
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felsabbagh3
|
36895d6e7c
|
Fixed miss_add on for snoop replays
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2020-03-29 21:21:53 -07:00 |
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Blaise Tine
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2d198a32c7
|
update
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2020-03-29 23:18:26 -04:00 |
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felsabbagh3
|
94cc2c10b1
|
Snoops shouldn't send fill requests
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2020-03-29 19:16:00 -07:00 |
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felsabbagh3
|
e31b2d6d7e
|
Fixed pulling signals from different stages
|
2020-03-29 18:17:01 -07:00 |
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felsabbagh3
|
d31116d584
|
Uses use_wb_valid instead of wb_req to include snoops
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2020-03-29 17:59:10 -07:00 |
|
felsabbagh3
|
71aae3e0a9
|
..
|
2020-03-29 17:28:57 -07:00 |
|
felsabbagh3
|
f96d77d75e
|
Mismatched vs matched
|
2020-03-29 17:18:57 -07:00 |
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felsabbagh3
|
a499bcd718
|
Added extra signals for debugging
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2020-03-29 17:04:17 -07:00 |
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felsabbagh3
|
95ee66f25a
|
Fixed Snoop Invalidate Logic
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2020-03-29 16:44:14 -07:00 |
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felsabbagh3
|
73390b9f58
|
b/unb error
|
2020-03-29 16:09:48 -07:00 |
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felsabbagh3
|
0a88c97485
|
Another reset issue...
|
2020-03-29 16:06:13 -07:00 |
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felsabbagh3
|
b99ba2c413
|
Removed scheduler_empty qualifier
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2020-03-29 15:24:50 -07:00 |
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felsabbagh3
|
eb6e0cee43
|
Fixing a bug in a fix...
|
2020-03-29 13:52:22 -07:00 |
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felsabbagh3
|
cd418a1f96
|
Mrvq stopping reqq popping added to avoid mrvq full deadlock
|
2020-03-29 13:19:06 -07:00 |
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felsabbagh3
|
f43a9ad1a6
|
Added proper resetting to cache
|
2020-03-29 10:57:32 -07:00 |
|
Blaise Tine
|
3a23e05a88
|
Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
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2020-03-29 05:24:48 -04:00 |
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Blaise Tine
|
ce0cc44d11
|
update
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2020-03-29 05:24:40 -04:00 |
|
felsabbagh3
|
efac643c66
|
Added Proper Handshaking to Everything and Fixed a Couple of Bugs
|
2020-03-29 02:11:14 -07:00 |
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felsabbagh3
|
d31b607e01
|
Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis
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2020-03-28 21:43:51 -07:00 |
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felsabbagh3
|
313a8e3b4b
|
All cache bugs fixed - Handshaking
|
2020-03-28 21:43:02 -07:00 |
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Blaise Tine
|
22be51b0c8
|
fixed multicore build
|
2020-03-28 01:40:26 -04:00 |
|
felsabbagh3
|
5dc9493c61
|
ALL tests passing - handshake
|
2020-03-27 21:34:49 -07:00 |
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Blaise Tine
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e80fa7f233
|
missing rtl changes from OPAE
|
2020-03-27 22:37:35 -04:00 |
|
Blaise Tine
|
8bb1f66220
|
missing rtl changes from OPAE
|
2020-03-27 22:37:35 -04:00 |
|
Blaise Tine
|
550d96a73c
|
rtlsim driver works with Vortex!
|
2020-03-27 21:54:55 -04:00 |
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