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All cache bugs fixed - Handshaking

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This commit is contained in:
felsabbagh3
2020-03-28 21:43:02 -07:00
parent 5dc9493c61 f7e0d1e491
commit 313a8e3b4b
301 changed files with 527762 additions and 30493 deletions
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44
rtl/Makefile
View File

@@ -1,32 +1,35 @@
all: RUNFILE
INCLUDE=-I. -Ishared_memory -Icache -IVX_cache -IVX_cache/interfaces -Iinterfaces/ -Ipipe_regs/ -Icompat/ -Isimulate
INCLUDE = -I. -Ishared_memory -Icache -IVX_cache -IVX_cache/interfaces -Iinterfaces/ -Ipipe_regs/ -Icompat/ -Isimulate
SINGLE_CORE=Vortex.v
MULTI_CORE=Vortex_SOC.v
SINGLE_CORE = Vortex.v
EXE=--exe ./simulate/test_bench.cpp
MULTI_EXE=--exe ./simulate/multi_test_bench.cpp
MULTI_CORE = Vortex_SOC.v
COMP=--compiler gcc --language 1800-2009
EXE += --exe ./simulate/test_bench.cpp ./simulate/Vortex.cpp
WNO=-Wno-UNDRIVEN --Wno-PINMISSING -Wno-STMTDLY -Wno-WIDTH -Wno-UNSIGNED -Wno-UNOPTFLAT -Wno-LITENDIAN
MULTI_EXE += --exe ./simulate/multi_test_bench.cpp ./simulate/Vortex_SOC.cpp
VF += -compiler gcc --language 1800-2009
WNO += -Wno-UNDRIVEN --Wno-PINMISSING -Wno-STMTDLY -Wno-WIDTH -Wno-UNSIGNED -Wno-UNOPTFLAT -Wno-LITENDIAN
# WNO=
# LIGHTW=
LIGHTW=-Wno-UNOPTFLAT
LIGHTW += -Wno-UNOPTFLAT
# LIB=-LDFLAGS '-L/usr/local/systemc/'
LIB=
LIB +=
CF = -std=c++11 -fms-extensions
CF += -std=c++11 -fms-extensions
DEB=--trace -DVL_DEBUG=1
DEB += --trace -DVL_DEBUG=1
MAKECPP=(cd obj_dir && make -j -f VVortex.mk OPT='-DVL_DEBUG' VL_DEBUG=1 DVL_DEBUG=1)
MAKECPP += (cd obj_dir && make -j -f VVortex.mk OPT='-DVL_DEBUG' VL_DEBUG=1 DVL_DEBUG=1)
MAKECPPRel=(cd obj_dir && make -j -f VVortex.mk)
MAKECPPRel += (cd obj_dir && make -j -f VVortex.mk)
MAKEMULTICPP=(cd obj_dir && make -j -f VVortex_SOC.mk OPT='-DVL_DEBUG' VL_DEBUG=1 DVL_DEBUG=1)
MAKEMULTICPP += (cd obj_dir && make -j -f VVortex_SOC.mk OPT='-DVL_DEBUG' VL_DEBUG=1 DVL_DEBUG=1)
THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))')
@@ -36,23 +39,22 @@ build_config:
# -LDFLAGS '-lsystemc'
VERILATOR: build_config
verilator $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OFF' $(LIGHTW)
verilator $(VF) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF)' $(LIGHTW)
VERILATORnoWarnings: build_config
verilator $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OFF' $(WNO) $(DEB)
verilator $(VF) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF)' $(WNO) $(DEB)
VERILATORnoWarningsRel: build_config
verilator $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OFF -O3 -DVL_THREADED' $(WNO) --threads $(THREADS)
verilator $(VF) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -O3 -DVL_THREADED' $(WNO) --threads $(THREADS)
VERILATORMULTInoWarnings: build_config
verilator $(COMP) -cc $(MULTI_CORE) $(INCLUDE) $(MULTI_EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OFF -O3 -DVL_THREADED' $(WNO) $(DEB) --threads $(THREADS)
verilator $(VF) -cc $(MULTI_CORE) $(INCLUDE) $(MULTI_EXE) $(LIB) -CFLAGS '$(CF) -O3 -DVL_THREADED' $(WNO) $(DEB) --threads $(THREADS)
compdebug: build_config
verilator_bin_dbg $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OUTPUT -DVL_DEBUG' $(WNO) $(DEB)
verilator_bin_dbg $(VF) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OUTPUT -DVL_DEBUG' $(WNO) $(DEB)
compdebugmulti: build_config
verilator_bin_dbg $(COMP) -cc $(MULTI_CORE) $(INCLUDE) $(MULTI_EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OUTPUT -DVL_DEBUG' $(WNO) $(DEB)
verilator_bin_dbg $(VF) -cc $(MULTI_CORE) $(INCLUDE) $(MULTI_EXE) $(LIB) -CFLAGS '$(CF) -DVCD_OUTPUT -DVL_DEBUG' $(WNO) $(DEB)
RUNFILE: VERILATOR
$(MAKECPP)

4
rtl/VX_cache/VX_bank.v
View File

@@ -558,7 +558,7 @@ module VX_bank
wire[`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] dwbq_req_data = readdata_st2;
wire dwbq_empty;
wire possible_fill = valid_st2 && miss_st2;
wire possible_fill = valid_st2 && miss_st2 && !dram_fill_req_queue_full;
wire[31:0] fill_invalidator_addr = addr_st2 & `BASE_ADDR_MASK;
VX_fill_invalidator #(
.CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),
@@ -590,7 +590,7 @@ module VX_bank
);
// Enqueu in dram_fill_req
assign dram_fill_req = valid_st2 && miss_st2 && !invalidate_fill && !dram_fill_req_queue_full;
assign dram_fill_req = possible_fill && !invalidate_fill;
assign dram_because_of_snp = is_snp_st2 && valid_st2 && miss_st2;
assign dram_snp_full = snrq_full && snp_req;
assign dram_fill_req_addr = addr_st2 & `BASE_ADDR_MASK;

96
rtl/VX_cache/VX_fill_invalidator.v
View File

@@ -68,35 +68,21 @@ module VX_fill_invalidator
reg[FILL_INVALIDAOR_SIZE-1:0][31:0] fills_address;
reg success_found;
reg[(`vx_clog2(FILL_INVALIDAOR_SIZE))-1:0] success_index;
integer curr_fill;
reg[FILL_INVALIDAOR_SIZE-1:0] matched_fill;
wire matched;
integer fi;
always @(*) begin
invalidate_fill = 0;
success_found = 0;
success_index = 0;
for (curr_fill = 0; curr_fill < FILL_INVALIDAOR_SIZE; curr_fill=curr_fill+1) begin
if (fill_addr[31:`LINE_SELECT_ADDR_START] == fills_address[curr_fill][31:`LINE_SELECT_ADDR_START]) begin
if (possible_fill && fills_active[curr_fill]) begin
invalidate_fill = 1;
end
if (success_fill) begin
success_found = 1;
success_index = curr_fill;
end
end
for (fi = 0; fi < FILL_INVALIDAOR_SIZE; fi+=1) begin
matched_fill[fi] = fills_active[fi] && (fills_address[fi][31:`LINE_SELECT_ADDR_START] == fill_addr[31:`LINE_SELECT_ADDR_START]);
end
end
assign matched = (|(matched_fill));
wire [(`vx_clog2(FILL_INVALIDAOR_SIZE))-1:0] enqueue_index;
wire [(`vx_clog2(FILL_INVALIDAOR_SIZE))-1:0] enqueue_index;
wire enqueue_found;
VX_generic_priority_encoder #(.N(FILL_INVALIDAOR_SIZE)) VX_sel_bank(
.valids(~fills_active),
.index (enqueue_index),
@@ -104,6 +90,7 @@ module VX_fill_invalidator
);
assign invalidate_fill = possible_fill && matched;
always @(posedge clk) begin
@@ -111,19 +98,74 @@ module VX_fill_invalidator
fills_active <= 0;
fills_address <= 0;
end else begin
if (possible_fill && !invalidate_fill) begin
fills_active[enqueue_index] <= 1;
fills_address[enqueue_index] <= fill_addr;
end
if (success_found) begin
fills_active[success_index] <= 0;
if (possible_fill && !matched && enqueue_found) begin
fills_active [enqueue_index] <= 1;
fills_address[enqueue_index] <= fill_addr;
end else if (success_fill && matched) begin
fills_active <= fills_active & (~matched_fill);
end
end
end
// reg success_found;
// reg[(`vx_clog2(FILL_INVALIDAOR_SIZE))-1:0] success_index;
// integer curr_fill;
// always @(*) begin
// invalidate_fill = 0;
// success_found = 0;
// success_index = 0;
// for (curr_fill = 0; curr_fill < FILL_INVALIDAOR_SIZE; curr_fill=curr_fill+1) begin
// if (fill_addr[31:`LINE_SELECT_ADDR_START] == fills_address[curr_fill][31:`LINE_SELECT_ADDR_START]) begin
// if (possible_fill && fills_active[curr_fill]) begin
// invalidate_fill = 1;
// end
// if (success_fill) begin
// success_found = 1;
// success_index = curr_fill;
// end
// end
// end
// end
// wire [(`vx_clog2(FILL_INVALIDAOR_SIZE))-1:0] enqueue_index;
// wire enqueue_found;
// VX_generic_priority_encoder #(.N(FILL_INVALIDAOR_SIZE)) VX_sel_bank(
// .valids(~fills_active),
// .index (enqueue_index),
// .found (enqueue_found)
// );
// always @(posedge clk) begin
// if (reset) begin
// fills_active <= 0;
// fills_address <= 0;
// end else begin
// if (possible_fill && !invalidate_fill) begin
// fills_active[enqueue_index] <= 1;
// fills_address[enqueue_index] <= fill_addr;
// end
// if (success_found) begin
// fills_active[success_index] <= 0;
// end
// end
// end
end

2
rtl/VX_cache/VX_tag_data_access.v
View File

@@ -249,7 +249,7 @@ module VX_tag_data_access
wire normal_write = (block_offset == g[`WORD_SELECT_SIZE_RNG]) && should_write && !real_writefill;
assign we[g] = (force_write) ? 4'b1111 :
(normal_write && (FUNC_ID == `LLFUNC_ID)) ? 4'b1111 :
(should_write && !real_writefill && (FUNC_ID == `LLFUNC_ID)) ? 4'b1111 :
(normal_write && sw) ? 4'b1111 :
(normal_write && sb) ? sb_mask :
(normal_write && sh) ? sh_mask :

38
rtl/VX_define.v
View File

@@ -162,7 +162,7 @@
// Size of cache in bytes
`ifndef DCACHE_SIZE_BYTES
`define DCACHE_SIZE_BYTES 4096
`define DCACHE_SIZE_BYTES 2048
`endif
// Size of line inside a bank in bytes
@@ -256,7 +256,7 @@
// Fill Invalidator Size {Fill invalidator must be active}
`ifndef DFILL_INVALIDAOR_SIZE
`define DFILL_INVALIDAOR_SIZE 0
`define DFILL_INVALIDAOR_SIZE 32
`endif
// Dram knobs
@@ -270,7 +270,7 @@
// Size of cache in bytes
`ifndef ICACHE_SIZE_BYTES
`define ICACHE_SIZE_BYTES 1024
`define ICACHE_SIZE_BYTES 4096
`endif
// Size of line inside a bank in bytes
@@ -364,7 +364,7 @@
// Fill Invalidator Size {Fill invalidator must be active}
`ifndef IFILL_INVALIDAOR_SIZE
`define IFILL_INVALIDAOR_SIZE 0
`define IFILL_INVALIDAOR_SIZE 32
`endif
// Dram knobs
@@ -470,7 +470,7 @@
// Fill Invalidator Size {Fill invalidator must be active}
`ifndef SFILL_INVALIDAOR_SIZE
`define SFILL_INVALIDAOR_SIZE 0
`define SFILL_INVALIDAOR_SIZE 32
`endif
// Dram knobs
@@ -484,7 +484,7 @@
// Size of cache in bytes
`ifndef LLCACHE_SIZE_BYTES
`define LLCACHE_SIZE_BYTES 1024
`define LLCACHE_SIZE_BYTES 4096
`endif
// Size of line inside a bank in bytes
@@ -528,12 +528,12 @@
// Core Request Queue Size
`ifndef LLREQQ_SIZE
`define LLREQQ_SIZE (2*`NUMBER_CORES_PER_CLUSTER)
`define LLREQQ_SIZE 32
`endif
// Miss Reserv Queue Knob
`ifndef LLMRVQ_SIZE
`define LLMRVQ_SIZE (`DNUMBER_BANKS*`NUMBER_CORES_PER_CLUSTER)
`define LLMRVQ_SIZE 32
`endif
// Dram Fill Rsp Queue Size
@@ -543,7 +543,7 @@
// Snoop Req Queue
`ifndef LLSNRQ_SIZE
`define LLSNRQ_SIZE 8
`define LLSNRQ_SIZE 32
`endif
// Queues for writebacks Knobs {1, 2, 4, 8, ...}
@@ -555,7 +555,7 @@
// Dram Writeback Queue Size
`ifndef LLDWBQ_SIZE
`define LLDWBQ_SIZE 4
`define LLDWBQ_SIZE 16
`endif
// Dram Fill Req Queue Size
@@ -565,17 +565,17 @@
// Lower Level Cache Hit Queue Size
`ifndef LLLLVQ_SIZE
`define LLLLVQ_SIZE 16
`define LLLLVQ_SIZE 32
`endif
// Fill Forward SNP Queue
`ifndef LLFFSQ_SIZE
`define LLFFSQ_SIZE 8
`define LLFFSQ_SIZE 32
`endif
// Fill Invalidator Size {Fill invalidator must be active}
`ifndef LLFILL_INVALIDAOR_SIZE
`define LLFILL_INVALIDAOR_SIZE 0
`define LLFILL_INVALIDAOR_SIZE 32
`endif
// Dram knobs
@@ -589,7 +589,7 @@
// Size of cache in bytes
`ifndef L3CACHE_SIZE_BYTES
`define L3CACHE_SIZE_BYTES 1024
`define L3CACHE_SIZE_BYTES 8192
`endif
// Size of line inside a bank in bytes
@@ -633,12 +633,12 @@
// Core Request Queue Size
`ifndef L3REQQ_SIZE
`define L3REQQ_SIZE (`NT*`NW*`NUMBER_CLUSTERS)
`define L3REQQ_SIZE 32
`endif
// Miss Reserv Queue Knob
`ifndef L3MRVQ_SIZE
`define L3MRVQ_SIZE `LLREQQ_SIZE
`define L3MRVQ_SIZE `L3REQQ_SIZE
`endif
// Dram Fill Rsp Queue Size
@@ -648,7 +648,7 @@
// Snoop Req Queue
`ifndef L3SNRQ_SIZE
`define L3SNRQ_SIZE 8
`define L3SNRQ_SIZE 32
`endif
// Queues for writebacks Knobs {1, 2, 4, 8, ...}
@@ -660,7 +660,7 @@
// Dram Writeback Queue Size
`ifndef L3DWBQ_SIZE
`define L3DWBQ_SIZE 4
`define L3DWBQ_SIZE 16
`endif
// Dram Fill Req Queue Size
@@ -680,7 +680,7 @@
// Fill Invalidator Size {Fill invalidator must be active}
`ifndef L3FILL_INVALIDAOR_SIZE
`define L3FILL_INVALIDAOR_SIZE 0
`define L3FILL_INVALIDAOR_SIZE 32
`endif
// Dram knobs

4
rtl/VX_fetch.v
View File

@@ -98,8 +98,8 @@ module VX_fetch (
assign fe_inst_meta_fi.instruction = 32'h0;
assign fe_inst_meta_fi.inst_pc = warp_pc;
wire start_mat_add = scheduled_warp && (warp_pc == 32'h80000e94) && (warp_num == 0);
wire end_mat_add = scheduled_warp && (warp_pc == 32'h80000ef0) && (warp_num == 0);
wire start_mat_add = scheduled_warp && (warp_pc == 32'h80000ed8) && (warp_num == 0);
wire end_mat_add = scheduled_warp && (warp_pc == 32'h80000fbc) && (warp_num == 0);
endmodule

2
rtl/VX_warp_scheduler.v
View File

@@ -298,7 +298,7 @@ module VX_warp_scheduler (
assign global_stall = (stall || wstall_this_cycle || hazard || !real_schedule || is_join);
assign scheduled_warp = !(wstall_this_cycle || hazard || !real_schedule || is_join);
assign scheduled_warp = !(wstall_this_cycle || hazard || !real_schedule || is_join) && !reset;
wire real_use_wspawn = use_wsapwn[warp_to_schedule];

1
rtl/Vortex.v
View File

@@ -30,7 +30,6 @@ module Vortex
input wire [31:0] dram_fill_rsp_addr,
input wire [31:0] dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG],
// DRAM Icache Req
output wire I_dram_req,
output wire I_dram_req_write,

8
rtl/Vortex_SOC.v
View File

@@ -369,11 +369,11 @@ module Vortex_SOC (
assign per_core_dram_fill_rsp_addr[(l2c_curr_core/2)] = l2c_wb_addr[l2c_curr_core];
assign per_core_I_dram_fill_rsp_addr[(l2c_curr_core/2)] = l2c_wb_addr[l2c_curr_core+1];
assign per_core_dcache_snp_req [(l2c_curr_core/2)] = l2c_snp_fwd;
assign per_core_dcache_snp_req_addr[(l2c_curr_core/2)] = l2c_snp_fwd_addr;
assign per_core_dcache_snp_req [(l2c_curr_core/2)] = l2c_snp_fwd;
assign per_core_dcache_snp_req_addr[(l2c_curr_core/2)] = l2c_snp_fwd_addr;
assign per_core_icache_snp_req [(l2c_curr_core/2)] = l2c_snp_fwd;
assign per_core_icache_snp_req_addr[(l2c_curr_core/2)] = l2c_snp_fwd_addr;
assign per_core_icache_snp_req [(l2c_curr_core/2)] = l2c_snp_fwd;
assign per_core_icache_snp_req_addr[(l2c_curr_core/2)] = l2c_snp_fwd_addr;
end
// endgenerate

5
rtl/shared_memory/VX_shared_memory_block.v
View File

@@ -29,6 +29,8 @@ module VX_shared_memory_block
`ifndef SYN
reg[SMB_WORDS_PER_READ-1:0][3:0][7:0] shared_memory[SMB_HEIGHT-1:0];
wire [$clog2(SMB_HEIGHT) - 1:0]reg_addr;
//wire need_to_write = (|we);
integer curr_ind;
@@ -48,8 +50,7 @@ module VX_shared_memory_block
if (we == 2'b11) shared_memory[reg_addr][3] <= wdata[3];
end
end
wire [$clog2(SMB_HEIGHT) - 1:0]reg_addr;
assign reg_addr = addr;
// always @(posedge clk)
// reg_addr <= addr;

313
rtl/simulate/Vortex.cpp Normal file
View File

@@ -0,0 +1,313 @@
#include "Vortex.h"
unsigned long time_stamp = 0;
double sc_time_stamp() {
return time_stamp / 1000.0;
}
Vortex::Vortex(RAM *ram)
: start_pc(0), curr_cycle(0), stop(true), unit_test(true), stats_static_inst(0), stats_dynamic_inst(-1),
stats_total_cycles(0), stats_fwd_stalls(0), stats_branch_stalls(0),
debug_state(0), ibus_state(0), dbus_state(0), debug_return(0),
debug_wait_num(0), debug_inst_num(0), debug_end_wait(0), debug_debugAddr(0) {
this->ram = ram;
this->vortex = new VVortex;
#ifdef VCD_OUTPUT
Verilated::traceEverOn(true);
this->m_trace = new VerilatedVcdC;
this->vortex->trace(m_trace, 99);
this->m_trace->open("trace.vcd");
#endif
this->results.open("../results.txt");
}
Vortex::~Vortex() {
#ifdef VCD_OUTPUT
m_trace->close();
#endif
this->results.close();
delete this->vortex;
}
void Vortex::print_stats(bool cycle_test) {
if (cycle_test) {
this->results << std::left;
// this->results << "# Static Instructions:\t" << std::dec << this->stats_static_inst << std::endl;
this->results << std::setw(24) << "# Dynamic Instructions:" << std::dec << this->stats_dynamic_inst << std::endl;
this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl;
this->results << std::setw(24) << "# of forwarding stalls:" << std::dec << this->stats_fwd_stalls << std::endl;
this->results << std::setw(24) << "# of branch stalls:" << std::dec << this->stats_branch_stalls << std::endl;
this->results << std::setw(24) << "# CPI:" << std::dec << (double)this->stats_total_cycles / (double)this->stats_dynamic_inst << std::endl;
this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl;
} else {
this->results << std::left;
this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl;
this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl;
}
uint32_t status;
ram->getWord(0, &status);
if (this->unit_test) {
if (status == 1) {
this->results << std::setw(24) << "# GRADE:"
<< "PASSING\n";
} else {
this->results << std::setw(24) << "# GRADE:"
<< "Failed on test: " << status << "\n";
}
} else {
this->results << std::setw(24) << "# GRADE:"
<< "N/A [NOT A UNIT TEST]\n";
}
this->stats_static_inst = 0;
this->stats_dynamic_inst = -1;
this->stats_total_cycles = 0;
this->stats_fwd_stalls = 0;
this->stats_branch_stalls = 0;
}
bool Vortex::ibus_driver() {
// Iterate through each element, and get pop index
int dequeue_index = -1;
bool dequeue_valid = false;
for (int i = 0; i < this->I_dram_req_vec.size(); i++) {
if (this->I_dram_req_vec[i].cycles_left > 0) {
this->I_dram_req_vec[i].cycles_left -= 1;
}
if ((this->I_dram_req_vec[i].cycles_left == 0) && (!dequeue_valid)) {
dequeue_index = i;
dequeue_valid = true;
}
}
if (vortex->I_dram_req) {
// std::cout << "Icache Dram Request received!\n";
if (vortex->I_dram_req_read) {
// std::cout << "Icache Dram Request is read!\n";
// Need to add an element
dram_req_t dram_req;
dram_req.cycles_left = vortex->I_dram_expected_lat;
dram_req.data_length = vortex->I_dram_req_size / 4;
dram_req.base_addr = vortex->I_dram_req_addr;
dram_req.data = (unsigned *)malloc(dram_req.data_length * sizeof(unsigned));
for (int i = 0; i < dram_req.data_length; i++) {
unsigned curr_addr = dram_req.base_addr + (i * 4);
unsigned data_rd;
ram->getWord(curr_addr, &data_rd);
dram_req.data[i] = data_rd;
}
// std::cout << "Fill Req -> Addr: " << std::hex << dram_req.base_addr << std::dec << "\n";
this->I_dram_req_vec.push_back(dram_req);
}
if (vortex->I_dram_req_write) {
unsigned base_addr = vortex->I_dram_req_addr;
unsigned data_length = vortex->I_dram_req_size / 4;
for (int i = 0; i < data_length; i++) {
unsigned curr_addr = base_addr + (i * 4);
unsigned data_wr = vortex->I_dram_req_data[i];
ram->writeWord(curr_addr, &data_wr);
}
}
}
if (vortex->I_dram_fill_accept && dequeue_valid) {
// std::cout << "Icache Dram Response Sending...!\n";
vortex->I_dram_fill_rsp = 1;
vortex->I_dram_fill_rsp_addr = this->I_dram_req_vec[dequeue_index].base_addr;
// std::cout << "Fill Rsp -> Addr: " << std::hex << (this->I_dram_req_vec[dequeue_index].base_addr) << std::dec << "\n";
for (int i = 0; i < this->I_dram_req_vec[dequeue_index].data_length; i++) {
vortex->I_dram_fill_rsp_data[i] = this->I_dram_req_vec[dequeue_index].data[i];
}
free(this->I_dram_req_vec[dequeue_index].data);
this->I_dram_req_vec.erase(this->I_dram_req_vec.begin() + dequeue_index);
} else {
vortex->I_dram_fill_rsp = 0;
vortex->I_dram_fill_rsp_addr = 0;
}
return false;
}
void Vortex::io_handler() {
// std::cout << "Checking\n";
if (vortex->io_valid) {
uint32_t data_write = (uint32_t)vortex->io_data;
// std::cout << "IO VALID!\n";
char c = (char)data_write;
std::cerr << c;
// std::cout << c;
std::cout << std::flush;
}
}
bool Vortex::dbus_driver() {
// Iterate through each element, and get pop index
int dequeue_index = -1;
bool dequeue_valid = false;
for (int i = 0; i < this->dram_req_vec.size(); i++) {
if (this->dram_req_vec[i].cycles_left > 0) {
this->dram_req_vec[i].cycles_left -= 1;
}
if ((this->dram_req_vec[i].cycles_left == 0) && (!dequeue_valid)) {
dequeue_index = i;
dequeue_valid = true;
}
}
if (vortex->dram_req) {
if (vortex->dram_req_read) {
// Need to add an element
dram_req_t dram_req;
dram_req.cycles_left = vortex->dram_expected_lat;
dram_req.data_length = vortex->dram_req_size / 4;
dram_req.base_addr = vortex->dram_req_addr;
dram_req.data = (unsigned *)malloc(dram_req.data_length * sizeof(unsigned));
for (int i = 0; i < dram_req.data_length; i++) {
unsigned curr_addr = dram_req.base_addr + (i * 4);
unsigned data_rd;
ram->getWord(curr_addr, &data_rd);
dram_req.data[i] = data_rd;
}
// std::cout << "Fill Req -> Addr: " << std::hex << dram_req.base_addr << std::dec << "\n";
this->dram_req_vec.push_back(dram_req);
}
if (vortex->dram_req_write) {
unsigned base_addr = vortex->dram_req_addr;
unsigned data_length = vortex->dram_req_size / 4;
for (int i = 0; i < data_length; i++) {
unsigned curr_addr = base_addr + (i * 4);
unsigned data_wr = vortex->dram_req_data[i];
ram->writeWord(curr_addr, &data_wr);
}
}
}
if (vortex->dram_fill_accept && dequeue_valid) {
vortex->dram_fill_rsp = 1;
vortex->dram_fill_rsp_addr = this->dram_req_vec[dequeue_index].base_addr;
// std::cout << "Fill Rsp -> Addr: " << std::hex << (this->dram_req_vec[dequeue_index].base_addr) << std::dec << "\n";
for (int i = 0; i < this->dram_req_vec[dequeue_index].data_length; i++) {
vortex->dram_fill_rsp_data[i] = this->dram_req_vec[dequeue_index].data[i];
}
free(this->dram_req_vec[dequeue_index].data);
this->dram_req_vec.erase(this->dram_req_vec.begin() + dequeue_index);
} else {
vortex->dram_fill_rsp = 0;
vortex->dram_fill_rsp_addr = 0;
}
return false;
}
void Vortex::reset() {
vortex->reset = 1;
this->step();
vortex->reset = 0;
}
void Vortex::step() {
vortex->clk = 0;
vortex->eval();
#ifdef VCD_OUTPUT
m_trace->dump(2 * this->stats_total_cycles + 0);
#endif
vortex->clk = 1;
vortex->eval();
ibus_driver();
dbus_driver();
io_handler();
#ifdef VCD_OUTPUT
m_trace->dump(2 * this->stats_total_cycles + 1);
#endif
++time_stamp;
++stats_total_cycles;
}
void Vortex::wait(uint32_t cycles) {
for (int i = 0; i < cycles; ++i) {
this->step();
}
}
bool Vortex::is_busy() {
return (0 == vortex->out_ebreak);
}
void Vortex::send_snoops(uint32_t mem_addr, uint32_t size) {
// align address to LLC block boundaries
auto aligned_addr_start = GLOBAL_BLOCK_SIZE_BYTES * ((mem_addr + GLOBAL_BLOCK_SIZE_BYTES - 1) / GLOBAL_BLOCK_SIZE_BYTES);
auto aligned_addr_end = GLOBAL_BLOCK_SIZE_BYTES * ((mem_addr + size + GLOBAL_BLOCK_SIZE_BYTES - 1) / GLOBAL_BLOCK_SIZE_BYTES);
// submit snoop requests for the needed blocks
vortex->snp_req_addr = aligned_addr_start;
vortex->snp_req = false;
for (;;) {
this->step();
if (vortex->snp_req) {
vortex->snp_req = false;
if (vortex->snp_req_addr >= aligned_addr_end)
break;
vortex->snp_req_addr += GLOBAL_BLOCK_SIZE_BYTES;
}
if (!vortex->snp_req_delay) {
vortex->snp_req = true;
}
}
}
void Vortex::flush_caches(uint32_t mem_addr, uint32_t size) {
// send snoops for L1 flush
this->send_snoops(mem_addr, size);
#if NUMBER_CORES != 1
// send snoops for L2 flush
this->send_snoops(mem_addr, size);
#endif
// wait 50 cycles to ensure that the request has committed
this->wait(50);
}
bool Vortex::simulate() {
// reset the device
this->reset();
// execute program
while (!vortex->out_ebreak) {
this->step();
}
// wait 5 cycles to flush the pipeline
this->wait(5);
std::cerr << "New Total Cycles: " << (this->stats_total_cycles) << "\n";
this->print_stats();
// check riscv-tests PASSED/FAILED status
int status = (unsigned int) vortex->Vortex->vx_back_end->VX_wb->last_data_wb & 0xf;
return (status == 1);
}

501
rtl/simulate/Vortex.h
View File

@@ -1,7 +1,7 @@
// C++ libraries
#include <utility>
#include <utility>
#include <iostream>
#include <map>
#include <map>
#include <iterator>
#include <iomanip>
#include <fstream>
@@ -20,446 +20,61 @@
#include <verilated_vcd_c.h>
#endif
unsigned long time_stamp = 0;
double sc_time_stamp()
{
return time_stamp / 1000.0;
}
typedef struct
{
int cycles_left;
int data_length;
unsigned base_addr;
unsigned * data;
typedef struct {
int cycles_left;
int data_length;
unsigned base_addr;
unsigned *data;
} dram_req_t;
class Vortex
{
public:
Vortex(RAM* ram);
~Vortex();
bool simulate();
private:
void print_stats(bool = true);
bool ibus_driver();
bool dbus_driver();
void io_handler();
RAM* ram;
VVortex * vortex;
unsigned start_pc;
bool refill_d;
unsigned refill_addr_d;
bool refill_i;
unsigned refill_addr_i;
long int curr_cycle;
bool stop;
bool unit_test;
std::ofstream results;
int stats_static_inst;
int stats_dynamic_inst;
int stats_total_cycles;
int stats_fwd_stalls;
int stats_branch_stalls;
int debug_state;
int ibus_state;
int dbus_state;
int debug_return;
int debug_wait_num;
int debug_inst_num;
int debug_end_wait;
int debug_debugAddr;
double stats_sim_time;
std::vector<dram_req_t> dram_req_vec;
std::vector<dram_req_t> I_dram_req_vec;
#ifdef VCD_OUTPUT
VerilatedVcdC *m_trace;
#endif
};
Vortex::Vortex(RAM* ram) : start_pc(0), curr_cycle(0), stop(true), unit_test(true), stats_static_inst(0), stats_dynamic_inst(-1),
stats_total_cycles(0), stats_fwd_stalls(0), stats_branch_stalls(0),
debug_state(0), ibus_state(0), dbus_state(0), debug_return(0),
debug_wait_num(0), debug_inst_num(0), debug_end_wait(0), debug_debugAddr(0)
{
this->ram = ram;
this->vortex = new VVortex;
#ifdef VCD_OUTPUT
this->m_trace = new VerilatedVcdC;
this->vortex->trace(m_trace, 99);
this->m_trace->open("trace.vcd");
#endif
this->results.open("../results.txt");
}
Vortex::~Vortex()
{
#ifdef VCD_OUTPUT
m_trace->close();
#endif
this->results.close();
delete this->vortex;
}
void Vortex::print_stats(bool cycle_test)
{
if (cycle_test)
{
this->results << std::left;
// this->results << "# Static Instructions:\t" << std::dec << this->stats_static_inst << std::endl;
this->results << std::setw(24) << "# Dynamic Instructions:" << std::dec << this->stats_dynamic_inst << std::endl;
this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl;
this->results << std::setw(24) << "# of forwarding stalls:" << std::dec << this->stats_fwd_stalls << std::endl;
this->results << std::setw(24) << "# of branch stalls:" << std::dec << this->stats_branch_stalls << std::endl;
this->results << std::setw(24) << "# CPI:" << std::dec << (double) this->stats_total_cycles / (double) this->stats_dynamic_inst << std::endl;
this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl;
}
else
{
this->results << std::left;
this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl;
this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl;
}
uint32_t status;
ram->getWord(0, &status);
if (this->unit_test)
{
if (status == 1)
{
this->results << std::setw(24) << "# GRADE:" << "PASSING\n";
} else
{
this->results << std::setw(24) << "# GRADE:" << "Failed on test: " << status << "\n";
}
}
else
{
this->results << std::setw(24) << "# GRADE:" << "N/A [NOT A UNIT TEST]\n";
}
this->stats_static_inst = 0;
this->stats_dynamic_inst = -1;
this->stats_total_cycles = 0;
this->stats_fwd_stalls = 0;
this->stats_branch_stalls = 0;
}
bool Vortex::ibus_driver()
{
// Iterate through each element, and get pop index
int dequeue_index = -1;
bool dequeue_valid = false;
for (int i = 0; i < this->I_dram_req_vec.size(); i++)
{
if (this->I_dram_req_vec[i].cycles_left > 0)
{
this->I_dram_req_vec[i].cycles_left -= 1;
}
if ((this->I_dram_req_vec[i].cycles_left == 0) && (!dequeue_valid))
{
dequeue_index = i;
dequeue_valid = true;
}
}
if (vortex->I_dram_req)
{
// std::cout << "Icache Dram Request received!\n";
if (vortex->I_dram_req_read)
{
// std::cout << "Icache Dram Request is read!\n";
// Need to add an element
dram_req_t dram_req;
dram_req.cycles_left = vortex->I_dram_expected_lat;
dram_req.data_length = vortex->I_dram_req_size / 4;
dram_req.base_addr = vortex->I_dram_req_addr;
dram_req.data = (unsigned *) malloc(dram_req.data_length * sizeof(unsigned));
for (int i = 0; i < dram_req.data_length; i++)
{
unsigned curr_addr = dram_req.base_addr + (i*4);
unsigned data_rd;
ram->getWord(curr_addr, &data_rd);
dram_req.data[i] = data_rd;
}
// std::cout << "Fill Req -> Addr: " << std::hex << dram_req.base_addr << std::dec << "\n";
this->I_dram_req_vec.push_back(dram_req);
}
if (vortex->I_dram_req_write)
{
unsigned base_addr = vortex->I_dram_req_addr;
unsigned data_length = vortex->I_dram_req_size / 4;
for (int i = 0; i < data_length; i++)
{
unsigned curr_addr = base_addr + (i*4);
unsigned data_wr = vortex->I_dram_req_data[i];
ram->writeWord(curr_addr, &data_wr);
}
}
}
if (vortex->I_dram_fill_accept && dequeue_valid)
{
// std::cout << "Icache Dram Response Sending...!\n";
vortex->I_dram_fill_rsp = 1;
vortex->I_dram_fill_rsp_addr = this->I_dram_req_vec[dequeue_index].base_addr;
// std::cout << "Fill Rsp -> Addr: " << std::hex << (this->I_dram_req_vec[dequeue_index].base_addr) << std::dec << "\n";
for (int i = 0; i < this->I_dram_req_vec[dequeue_index].data_length; i++)
{
vortex->I_dram_fill_rsp_data[i] = this->I_dram_req_vec[dequeue_index].data[i];
}
free(this->I_dram_req_vec[dequeue_index].data);
this->I_dram_req_vec.erase(this->I_dram_req_vec.begin() + dequeue_index);
}
else
{
vortex->I_dram_fill_rsp = 0;
vortex->I_dram_fill_rsp_addr = 0;
}
return false;
}
void Vortex::io_handler()
{
// std::cout << "Checking\n";
if (vortex->io_valid)
{
uint32_t data_write = (uint32_t) vortex->io_data;
// std::cout << "IO VALID!\n";
char c = (char) data_write;
std::cerr << c;
// std::cout << c;
std::cout << std::flush;
}
}
bool Vortex::dbus_driver()
{
// Iterate through each element, and get pop index
int dequeue_index = -1;
bool dequeue_valid = false;
for (int i = 0; i < this->dram_req_vec.size(); i++)
{
if (this->dram_req_vec[i].cycles_left > 0)
{
this->dram_req_vec[i].cycles_left -= 1;
}
if ((this->dram_req_vec[i].cycles_left == 0) && (!dequeue_valid))
{
dequeue_index = i;
dequeue_valid = true;
}
}
if (vortex->dram_req)
{
if (vortex->dram_req_read)
{
// Need to add an element
dram_req_t dram_req;
dram_req.cycles_left = vortex->dram_expected_lat;
dram_req.data_length = vortex->dram_req_size / 4;
dram_req.base_addr = vortex->dram_req_addr;
dram_req.data = (unsigned *) malloc(dram_req.data_length * sizeof(unsigned));
for (int i = 0; i < dram_req.data_length; i++)
{
unsigned curr_addr = dram_req.base_addr + (i*4);
unsigned data_rd;
ram->getWord(curr_addr, &data_rd);
dram_req.data[i] = data_rd;
}
// std::cout << "Fill Req -> Addr: " << std::hex << dram_req.base_addr << std::dec << "\n";
this->dram_req_vec.push_back(dram_req);
}
if (vortex->dram_req_write)
{
unsigned base_addr = vortex->dram_req_addr;
unsigned data_length = vortex->dram_req_size / 4;
for (int i = 0; i < data_length; i++)
{
unsigned curr_addr = base_addr + (i*4);
unsigned data_wr = vortex->dram_req_data[i];
ram->writeWord(curr_addr, &data_wr);
}
}
}
if (vortex->dram_fill_accept && dequeue_valid)
{
vortex->dram_fill_rsp = 1;
vortex->dram_fill_rsp_addr = this->dram_req_vec[dequeue_index].base_addr;
// std::cout << "Fill Rsp -> Addr: " << std::hex << (this->dram_req_vec[dequeue_index].base_addr) << std::dec << "\n";
for (int i = 0; i < this->dram_req_vec[dequeue_index].data_length; i++)
{
vortex->dram_fill_rsp_data[i] = this->dram_req_vec[dequeue_index].data[i];
}
free(this->dram_req_vec[dequeue_index].data);
this->dram_req_vec.erase(this->dram_req_vec.begin() + dequeue_index);
}
else
{
vortex->dram_fill_rsp = 0;
vortex->dram_fill_rsp_addr = 0;
}
return false;
}
bool Vortex::simulate()
{
// auto start_time = std::chrono::high_resolution_clock::now();
static bool stop = false;
static int counter = 0;
counter = 0;
stop = false;
// auto start_time = clock();
// vortex->reset = 1;
// vortex->reset = 0;
unsigned curr_inst;
unsigned new_PC;
// while (this->stop && (!(stop && (counter > 5))))
// {
// // std::cout << "************* Cycle: " << cycle << "\n";
// bool istop = ibus_driver();
// bool dstop = !dbus_driver();
// vortex->clk = 1;
// vortex->eval();
// vortex->clk = 0;
// vortex->eval();
// stop = istop && dstop;
// if (stop)
// {
// counter++;
// } else
// {
// counter = 0;
// }
// cycle++;
// }
bool istop;
bool dstop;
bool cont = false;
// for (int i = 0; i < 500; i++)
vortex->reset = 1;
vortex->clk = 0;
vortex->eval();
// m_trace->dump(10);
vortex->reset = 1;
vortex->clk = 1;
vortex->eval();
// m_trace->dump(11);
vortex->reset = 0;
vortex->clk = 0;
// unsigned cycles;
counter = 0;
this->stats_total_cycles = 12;
while (this->stop && ((counter < 5)))
// while (this->stats_total_cycles < 10)
{
// printf("-------------------------\n");
// std::cout << "Counter: " << counter << "\n";
// if ((this->stats_total_cycles) % 5000 == 0) std::cout << "************* Cycle: " << (this->stats_total_cycles) << "\n";
// dstop = !dbus_driver();
#ifdef VCD_OUTPUT
m_trace->dump(2*this->stats_total_cycles);
#endif
vortex->clk = 1;
vortex->eval();
istop = ibus_driver();
dstop = !dbus_driver();
io_handler();
#ifdef VCD_OUTPUT
m_trace->dump((2*this->stats_total_cycles)+1);
#endif
vortex->clk = 0;
vortex->eval();
// stop = istop && dstop;
stop = vortex->out_ebreak;
if (stop || cont)
// if (istop)
{
cont = true;
counter++;
} else
{
counter = 0;
}
++time_stamp;
++stats_total_cycles;
}
std::cerr << "New Total Cycles: " << (this->stats_total_cycles) << "\n";
int status = (unsigned int) vortex->Vortex->vx_back_end->VX_wb->last_data_wb & 0xf;
// std::cout << "Last wb: " << std::hex << ((unsigned int) vortex->Vortex__DOT__vx_back_end__DOT__VX_wb__DOT__last_data_wb) << "\n";
// std::cout << "Something: " << result << '\n';
// uint32_t status;
// ram->getWord(0, &status);
this->print_stats();
return (status == 1);
// return (1 == 1);
}
class Vortex {
public:
Vortex(RAM *ram);
~Vortex();
bool is_busy();
void reset();
void step();
void flush_caches(uint32_t mem_addr, uint32_t size);
bool simulate();
private:
void print_stats(bool cycle_test = true);
bool ibus_driver();
bool dbus_driver();
void io_handler();
void send_snoops(uint32_t mem_addr, uint32_t size);
void wait(uint32_t cycles);
RAM *ram;
VVortex *vortex;
unsigned start_pc;
bool refill_d;
unsigned refill_addr_d;
bool refill_i;
unsigned refill_addr_i;
long int curr_cycle;
bool stop;
bool unit_test;
std::ofstream results;
int stats_static_inst;
int stats_dynamic_inst;
int stats_total_cycles;
int stats_fwd_stalls;
int stats_branch_stalls;
int debug_state;
int ibus_state;
int dbus_state;
int debug_return;
int debug_wait_num;
int debug_inst_num;
int debug_end_wait;
int debug_debugAddr;
double stats_sim_time;
std::vector<dram_req_t> dram_req_vec;
std::vector<dram_req_t> I_dram_req_vec;
#ifdef VCD_OUTPUT
VerilatedVcdC *m_trace;
#endif
};

248
rtl/simulate/Vortex_SOC.cpp Normal file
View File

@@ -0,0 +1,248 @@
#include "Vortex_SOC.h"
unsigned long time_stamp = 0;
double sc_time_stamp() {
return time_stamp / 1000.0;
}
Vortex_SOC::Vortex_SOC(RAM *ram)
: start_pc(0), curr_cycle(0), stop(true), unit_test(true), stats_static_inst(0), stats_dynamic_inst(-1),
stats_total_cycles(0), stats_fwd_stalls(0), stats_branch_stalls(0),
debug_state(0), ibus_state(0), dbus_state(0), debug_return(0),
debug_wait_num(0), debug_inst_num(0), debug_end_wait(0), debug_debugAddr(0) {
this->ram = ram;
this->vortex = new VVortex_SOC;
#ifdef VCD_OUTPUT
Verilated::traceEverOn(true);
this->m_trace = new VerilatedVcdC;
this->vortex->trace(m_trace, 99);
this->m_trace->open("trace.vcd");
#endif
this->results.open("../results.txt");
}
Vortex_SOC::~Vortex_SOC() {
#ifdef VCD_OUTPUT
m_trace->close();
#endif
this->results.close();
delete this->vortex;
}
void Vortex_SOC::print_stats(bool cycle_test) {
if (cycle_test) {
this->results << std::left;
// this->results << "# Static Instructions:\t" << std::dec << this->stats_static_inst << std::endl;
this->results << std::setw(24) << "# Dynamic Instructions:" << std::dec << this->stats_dynamic_inst << std::endl;
this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl;
this->results << std::setw(24) << "# of forwarding stalls:" << std::dec << this->stats_fwd_stalls << std::endl;
this->results << std::setw(24) << "# of branch stalls:" << std::dec << this->stats_branch_stalls << std::endl;
this->results << std::setw(24) << "# CPI:" << std::dec << (double)this->stats_total_cycles / (double)this->stats_dynamic_inst << std::endl;
this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl;
} else {
this->results << std::left;
this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl;
this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl;
}
uint32_t status;
ram->getWord(0, &status);
if (this->unit_test) {
if (status == 1) {
this->results << std::setw(24) << "# GRADE:"
<< "PASSING\n";
} else {
this->results << std::setw(24) << "# GRADE:"
<< "Failed on test: " << status << "\n";
}
} else {
this->results << std::setw(24) << "# GRADE:"
<< "N/A [NOT A UNIT TEST]\n";
}
this->stats_static_inst = 0;
this->stats_dynamic_inst = -1;
this->stats_total_cycles = 0;
this->stats_fwd_stalls = 0;
this->stats_branch_stalls = 0;
}
bool Vortex_SOC::ibus_driver() {
return false;
}
void Vortex_SOC::io_handler() {
// std::cout << "Checking\n";
for (int c = 0; c < vortex->number_cores; c++) {
if (vortex->io_valid[c]) {
uint32_t data_write = (uint32_t)vortex->io_data[c];
// std::cout << "IO VALID!\n";
char c = (char)data_write;
std::cerr << c;
// std::cout << c;
std::cout << std::flush;
}
}
}
bool Vortex_SOC::dbus_driver() {
// Iterate through each element, and get pop index
int dequeue_index = -1;
bool dequeue_valid = false;
for (int i = 0; i < this->dram_req_vec.size(); i++) {
if (this->dram_req_vec[i].cycles_left > 0) {
this->dram_req_vec[i].cycles_left -= 1;
}
if ((this->dram_req_vec[i].cycles_left == 0) && (!dequeue_valid)) {
dequeue_index = i;
dequeue_valid = true;
}
}
if (vortex->out_dram_req) {
if (vortex->out_dram_req_read) {
// Need to add an element
dram_req_t dram_req;
dram_req.cycles_left = vortex->out_dram_expected_lat;
dram_req.data_length = vortex->out_dram_req_size / 4;
dram_req.base_addr = vortex->out_dram_req_addr;
dram_req.data = (unsigned *)malloc(dram_req.data_length * sizeof(unsigned));
for (int i = 0; i < dram_req.data_length; i++) {
unsigned curr_addr = dram_req.base_addr + (i * 4);
unsigned data_rd;
ram->getWord(curr_addr, &data_rd);
dram_req.data[i] = data_rd;
}
// std::cout << "Fill Req -> Addr: " << std::hex << dram_req.base_addr << std::dec << "\n";
this->dram_req_vec.push_back(dram_req);
}
if (vortex->out_dram_req_write) {
unsigned base_addr = vortex->out_dram_req_addr;
unsigned data_length = vortex->out_dram_req_size / 4;
for (int i = 0; i < data_length; i++) {
unsigned curr_addr = base_addr + (i * 4);
unsigned data_wr = vortex->out_dram_req_data[i];
ram->writeWord(curr_addr, &data_wr);
}
}
}
if (vortex->out_dram_fill_accept && dequeue_valid) {
vortex->out_dram_fill_rsp = 1;
vortex->out_dram_fill_rsp_addr = this->dram_req_vec[dequeue_index].base_addr;
// std::cout << "Fill Rsp -> Addr: " << std::hex << (this->dram_req_vec[dequeue_index].base_addr) << std::dec << "\n";
for (int i = 0; i < this->dram_req_vec[dequeue_index].data_length; i++) {
vortex->out_dram_fill_rsp_data[i] = this->dram_req_vec[dequeue_index].data[i];
}
free(this->dram_req_vec[dequeue_index].data);
this->dram_req_vec.erase(this->dram_req_vec.begin() + dequeue_index);
} else {
vortex->out_dram_fill_rsp = 0;
vortex->out_dram_fill_rsp_addr = 0;
}
return false;
}
void Vortex_SOC::reset() {
vortex->reset = 1;
this->step();
vortex->reset = 0;
}
void Vortex_SOC::step() {
vortex->clk = 0;
vortex->eval();
#ifdef VCD_OUTPUT
m_trace->dump(2 * this->stats_total_cycles + 0);
#endif
vortex->clk = 1;
vortex->eval();
ibus_driver();
dbus_driver();
io_handler();
#ifdef VCD_OUTPUT
m_trace->dump(2 * this->stats_total_cycles + 1);
#endif
++time_stamp;
++stats_total_cycles;
}
void Vortex_SOC::wait(uint32_t cycles) {
for (int i = 0; i < cycles; ++i) {
this->step();
}
}
bool Vortex_SOC::is_busy() {
return (0 == vortex->out_ebreak);
}
void Vortex_SOC::send_snoops(uint32_t mem_addr, uint32_t size) {
// align address to LLC block boundaries
auto aligned_addr_start = GLOBAL_BLOCK_SIZE_BYTES * ((mem_addr + GLOBAL_BLOCK_SIZE_BYTES - 1) / GLOBAL_BLOCK_SIZE_BYTES);
auto aligned_addr_end = GLOBAL_BLOCK_SIZE_BYTES * ((mem_addr + size + GLOBAL_BLOCK_SIZE_BYTES - 1) / GLOBAL_BLOCK_SIZE_BYTES);
// submit snoop requests for the needed blocks
vortex->llc_snp_req_addr = aligned_addr_start;
vortex->llc_snp_req = false;
for (;;) {
this->step();
if (vortex->llc_snp_req) {
vortex->llc_snp_req = false;
if (vortex->llc_snp_req_addr >= aligned_addr_end)
break;
vortex->llc_snp_req_addr += GLOBAL_BLOCK_SIZE_BYTES;
}
if (!vortex->llc_snp_req_delay) {
vortex->llc_snp_req = true;
}
}
}
void Vortex_SOC::flush_caches(uint32_t mem_addr, uint32_t size) {
// send snoops for L1 flush
this->send_snoops(mem_addr, size);
#if NUMBER_CORES != 1
// send snoops for L2 flush
this->send_snoops(mem_addr, size);
#endif
// wait 50 cycles to ensure that the request has committed
this->wait(50);
}
bool Vortex_SOC::simulate() {
// reset the device
this->reset();
// execute program
while (!vortex->out_ebreak) {
this->step();
}
// wait 5 cycles to flush the pipeline
this->wait(5);
std::cerr << "New Total Cycles: " << (this->stats_total_cycles) << "\n";
this->print_stats();
return false;
}

416
rtl/simulate/Vortex_SOC.h
View File

@@ -1,7 +1,7 @@
// C++ libraries
#include <utility>
#include <utility>
#include <iostream>
#include <map>
#include <map>
#include <iterator>
#include <iomanip>
#include <fstream>
@@ -19,371 +19,59 @@
#include <verilated_vcd_c.h>
#endif
unsigned long time_stamp = 0;
double sc_time_stamp()
{
return time_stamp / 1000.0;
}
typedef struct
{
int cycles_left;
int data_length;
unsigned base_addr;
unsigned * data;
typedef struct {
int cycles_left;
int data_length;
unsigned base_addr;
unsigned *data;
} dram_req_t;
class Vortex_SOC
{
public:
Vortex_SOC(RAM* ram);
~Vortex_SOC();
bool simulate();
private:
void print_stats(bool = true);
bool ibus_driver();
bool dbus_driver();
void io_handler();
class Vortex_SOC {
public:
Vortex_SOC(RAM *ram);
~Vortex_SOC();
bool is_busy();
void reset();
void step();
void flush_caches(uint32_t mem_addr, uint32_t size);
bool simulate();
private:
void print_stats(bool cycle_test = true);
bool ibus_driver();
bool dbus_driver();
void io_handler();
void send_snoops(uint32_t mem_addr, uint32_t size);
void wait(uint32_t cycles);
RAM* ram;
RAM *ram;
VVortex_SOC * vortex;
VVortex_SOC *vortex;
unsigned start_pc;
bool refill_d;
unsigned refill_addr_d;
bool refill_i;
unsigned refill_addr_i;
long int curr_cycle;
bool stop;
bool unit_test;
std::ofstream results;
int stats_static_inst;
int stats_dynamic_inst;
int stats_total_cycles;
int stats_fwd_stalls;
int stats_branch_stalls;
int debug_state;
int ibus_state;
int dbus_state;
int debug_return;
int debug_wait_num;
int debug_inst_num;
int debug_end_wait;
int debug_debugAddr;
double stats_sim_time;
std::vector<dram_req_t> dram_req_vec;
#ifdef VCD_OUTPUT
VerilatedVcdC *m_trace;
#endif
unsigned start_pc;
bool refill_d;
unsigned refill_addr_d;
bool refill_i;
unsigned refill_addr_i;
long int curr_cycle;
bool stop;
bool unit_test;
std::ofstream results;
int stats_static_inst;
int stats_dynamic_inst;
int stats_total_cycles;
int stats_fwd_stalls;
int stats_branch_stalls;
int debug_state;
int ibus_state;
int dbus_state;
int debug_return;
int debug_wait_num;
int debug_inst_num;
int debug_end_wait;
int debug_debugAddr;
double stats_sim_time;
std::vector<dram_req_t> dram_req_vec;
#ifdef VCD_OUTPUT
VerilatedVcdC *m_trace;
#endif
};
Vortex_SOC::Vortex_SOC(RAM* ram) : start_pc(0), curr_cycle(0), stop(true), unit_test(true), stats_static_inst(0), stats_dynamic_inst(-1),
stats_total_cycles(0), stats_fwd_stalls(0), stats_branch_stalls(0),
debug_state(0), ibus_state(0), dbus_state(0), debug_return(0),
debug_wait_num(0), debug_inst_num(0), debug_end_wait(0), debug_debugAddr(0)
{
this->ram = ram;
this->vortex = new VVortex_SOC;
#ifdef VCD_OUTPUT
this->m_trace = new VerilatedVcdC;
this->vortex->trace(m_trace, 99);
this->m_trace->open("trace.vcd");
#endif
this->results.open("../results.txt");
}
Vortex_SOC::~Vortex_SOC()
{
#ifdef VCD_OUTPUT
m_trace->close();
#endif
this->results.close();
delete this->vortex;
}
void Vortex_SOC::print_stats(bool cycle_test)
{
if (cycle_test)
{
this->results << std::left;
// this->results << "# Static Instructions:\t" << std::dec << this->stats_static_inst << std::endl;
this->results << std::setw(24) << "# Dynamic Instructions:" << std::dec << this->stats_dynamic_inst << std::endl;
this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl;
this->results << std::setw(24) << "# of forwarding stalls:" << std::dec << this->stats_fwd_stalls << std::endl;
this->results << std::setw(24) << "# of branch stalls:" << std::dec << this->stats_branch_stalls << std::endl;
this->results << std::setw(24) << "# CPI:" << std::dec << (double) this->stats_total_cycles / (double) this->stats_dynamic_inst << std::endl;
this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl;
}
else
{
this->results << std::left;
this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl;
this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl;
}
uint32_t status;
ram->getWord(0, &status);
if (this->unit_test)
{
if (status == 1)
{
this->results << std::setw(24) << "# GRADE:" << "PASSING\n";
} else
{
this->results << std::setw(24) << "# GRADE:" << "Failed on test: " << status << "\n";
}
}
else
{
this->results << std::setw(24) << "# GRADE:" << "N/A [NOT A UNIT TEST]\n";
}
this->stats_static_inst = 0;
this->stats_dynamic_inst = -1;
this->stats_total_cycles = 0;
this->stats_fwd_stalls = 0;
this->stats_branch_stalls = 0;
}
bool Vortex_SOC::ibus_driver()
{
return false;
}
void Vortex_SOC::io_handler()
{
// std::cout << "Checking\n";
for (int c = 0; c < vortex->number_cores; c++)
{
if (vortex->io_valid[c])
{
uint32_t data_write = (uint32_t) vortex->io_data[c];
// std::cout << "IO VALID!\n";
char c = (char) data_write;
std::cerr << c;
// std::cout << c;
std::cout << std::flush;
}
}
}
bool Vortex_SOC::dbus_driver()
{
// Iterate through each element, and get pop index
int dequeue_index = -1;
bool dequeue_valid = false;
for (int i = 0; i < this->dram_req_vec.size(); i++)
{
if (this->dram_req_vec[i].cycles_left > 0)
{
this->dram_req_vec[i].cycles_left -= 1;
}
if ((this->dram_req_vec[i].cycles_left == 0) && (!dequeue_valid))
{
dequeue_index = i;
dequeue_valid = true;
}
}
if (vortex->out_dram_req)
{
if (vortex->out_dram_req_read)
{
// Need to add an element
dram_req_t dram_req;
dram_req.cycles_left = vortex->out_dram_expected_lat;
dram_req.data_length = vortex->out_dram_req_size / 4;
dram_req.base_addr = vortex->out_dram_req_addr;
dram_req.data = (unsigned *) malloc(dram_req.data_length * sizeof(unsigned));
for (int i = 0; i < dram_req.data_length; i++)
{
unsigned curr_addr = dram_req.base_addr + (i*4);
unsigned data_rd;
ram->getWord(curr_addr, &data_rd);
dram_req.data[i] = data_rd;
}
// std::cout << "Fill Req -> Addr: " << std::hex << dram_req.base_addr << std::dec << "\n";
this->dram_req_vec.push_back(dram_req);
}
if (vortex->out_dram_req_write)
{
unsigned base_addr = vortex->out_dram_req_addr;
unsigned data_length = vortex->out_dram_req_size / 4;
for (int i = 0; i < data_length; i++)
{
unsigned curr_addr = base_addr + (i*4);
unsigned data_wr = vortex->out_dram_req_data[i];
ram->writeWord(curr_addr, &data_wr);
}
}
}
if (vortex->out_dram_fill_accept && dequeue_valid)
{
vortex->out_dram_fill_rsp = 1;
vortex->out_dram_fill_rsp_addr = this->dram_req_vec[dequeue_index].base_addr;
// std::cout << "Fill Rsp -> Addr: " << std::hex << (this->dram_req_vec[dequeue_index].base_addr) << std::dec << "\n";
for (int i = 0; i < this->dram_req_vec[dequeue_index].data_length; i++)
{
vortex->out_dram_fill_rsp_data[i] = this->dram_req_vec[dequeue_index].data[i];
}
free(this->dram_req_vec[dequeue_index].data);
this->dram_req_vec.erase(this->dram_req_vec.begin() + dequeue_index);
}
else
{
vortex->out_dram_fill_rsp = 0;
vortex->out_dram_fill_rsp_addr = 0;
}
return false;
}
bool Vortex_SOC::simulate()
{
// auto start_time = std::chrono::high_resolution_clock::now();
static bool stop = false;
static int counter = 0;
counter = 0;
stop = false;
// auto start_time = clock();
// vortex->reset = 1;
// vortex->reset = 0;
unsigned curr_inst;
unsigned new_PC;
// while (this->stop && (!(stop && (counter > 5))))
// {
// // std::cout << "************* Cycle: " << cycle << "\n";
// bool istop = ibus_driver();
// bool dstop = !dbus_driver();
// vortex->clk = 1;
// vortex->eval();
// vortex->clk = 0;
// vortex->eval();
// stop = istop && dstop;
// if (stop)
// {
// counter++;
// } else
// {
// counter = 0;
// }
// cycle++;
// }
bool istop;
bool dstop;
bool cont = false;
// for (int i = 0; i < 500; i++)
vortex->reset = 1;
vortex->clk = 0;
vortex->eval();
// m_trace->dump(10);
vortex->reset = 1;
vortex->clk = 1;
vortex->eval();
// m_trace->dump(11);
vortex->reset = 0;
vortex->clk = 0;
// unsigned cycles;
counter = 0;
this->stats_total_cycles = 12;
while (this->stop && ((counter < 5)))
// while (this->stats_total_cycles < 10)
{
// printf("-------------------------\n");
// std::cout << "Counter: " << counter << "\n";
// if ((this->stats_total_cycles) % 5000 == 0) std::cout << "************* Cycle: " << (this->stats_total_cycles) << "\n";
// dstop = !dbus_driver();
#ifdef VCD_OUTPUT
m_trace->dump(2*this->stats_total_cycles);
#endif
vortex->clk = 1;
vortex->eval();
istop = ibus_driver();
dstop = !dbus_driver();
io_handler();
#ifdef VCD_OUTPUT
m_trace->dump((2*this->stats_total_cycles)+1);
#endif
vortex->clk = 0;
vortex->eval();
// stop = istop && dstop;
stop = vortex->out_ebreak;
if (stop || cont)
// if (istop)
{
cont = true;
counter++;
} else
{
counter = 0;
}
++time_stamp;
++stats_total_cycles;
}
std::cerr << "New Total Cycles: " << (this->stats_total_cycles) << "\n";
int status = 0;
// int status = (unsigned int) vortex->Vortex_SOC__DOT__vx_back_end__DOT__VX_wb__DOT__last_data_wb & 0xf;
// std::cout << "Last wb: " << std::hex << ((unsigned int) vortex->Vortex__DOT__vx_back_end__DOT__VX_wb__DOT__last_data_wb) << "\n";
// std::cout << "Something: " << result << '\n';
// uint32_t status;
// ram->getWord(0, &status);
this->print_stats();
return (status == 1);
// return (1 == 1);
}

5
rtl/simulate/multi_test_bench.cpp
View File

@@ -5,13 +5,8 @@
int main(int argc, char **argv)
{
// Verilated::debug(1);
Verilated::commandArgs(argc, argv);
Verilated::traceEverOn(true);
// #define ALL_TESTS
#ifdef ALL_TESTS
bool passed = true;

1
rtl/simulate/tb_debug.h
View File

@@ -1 +0,0 @@
#define VCD_OFF

3
rtl/simulate/test_bench.cpp
View File

@@ -9,9 +9,6 @@ int main(int argc, char **argv)
Verilated::commandArgs(argc, argv);
Verilated::traceEverOn(true);
// #define ALL_TESTS
#ifdef ALL_TESTS
bool passed = true;