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Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis

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This commit is contained in:
felsabbagh3
2020-04-04 10:14:24 -07:00
parent 70bd673031 0a8d829f15
commit a7a1906bea
23 changed files with 218 additions and 123 deletions
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7
rtl/VX_cache/VX_cache_dram_req_arb.v
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@@ -82,6 +82,9 @@ module VX_cache_dram_req_arb
wire pref_pop;
wire pref_valid;
wire[31:0] pref_addr;
wire dwb_valid;
wire dfqq_req;
assign pref_pop = !dwb_valid && !dfqq_req && !dram_req_delay && pref_valid;
VX_prefetcher #(
@@ -105,10 +108,8 @@ module VX_cache_dram_req_arb
);
wire dfqq_req;
wire[31:0] dfqq_req_addr;
wire dfqq_empty;
wire dwb_valid;
wire dfqq_empty;
wire dfqq_pop = !dwb_valid && dfqq_req && !dram_req_delay; // If no dwb, and dfqq has valids, then pop
wire dfqq_push = (|per_bank_dram_fill_req);

66
rtl/VX_generic_queue_ll.v
View File

@@ -6,45 +6,47 @@ module VX_generic_queue_ll
parameter SIZE = 277
)
(
input wire clk,
input wire reset,
input wire push,
input wire[DATAW-1:0] in_data,
input wire clk,
input wire reset,
input wire push,
input wire [DATAW-1:0] in_data,
input wire pop,
output wire[DATAW-1:0] out_data,
output wire empty,
output wire full
);
input wire pop,
output wire [DATAW-1:0] out_data,
output wire empty,
output wire full
);
/* verilator lint_off WIDTH */
if (SIZE == 0) begin
assign empty = 1;
assign out_data = 0;
assign full = 0;
end else begin
`ifdef QUEUE_FORCE_MLAB
end else begin // (SIZE > 0)
`ifdef QUEUE_FORCE_MLAB
(* syn_ramstyle = "mlab" *) reg[DATAW-1:0] data[SIZE-1:0];
`else
reg[DATAW-1:0] data[SIZE-1:0];
`endif
`else
reg[ DATAW-1:0] data[SIZE-1:0];
`endif
reg[DATAW-1:0] curr_r, head_r;
reg[$clog2(SIZE+1)-1:0] size_r;
reg[$clog2(SIZE)-1:0] wr_ctr_r;
reg[$clog2(SIZE)-1:0] rd_ptr_r, rd_next_ptr_r;
reg empty_r, full_r, bypass_r;
wire reading, writing;
reg [DATAW-1:0] head_r;
reg [$clog2(SIZE+1)-1:0] size_r;
wire reading;
wire writing;
assign reading = pop && !empty;
assign writing = push && !full;
if (SIZE == 1) begin
always @(posedge clk) begin
if (reset) begin
size_r <= 0;
size_r <= 0;
head_r <= 0;
end else begin
if (writing && !reading) begin
size_r <= 1;
@@ -59,9 +61,19 @@ module VX_generic_queue_ll
end
assign out_data = head_r;
assign empty = (size_r == 0);
assign full = (size_r != 0) && !pop;
end else begin
assign empty = (size_r == 0);
assign full = (size_r != 0) && !pop;
end else begin // (SIZE > 1)
reg [DATAW-1:0] curr_r;
reg [$clog2(SIZE)-1:0] wr_ctr_r;
reg [$clog2(SIZE)-1:0] rd_ptr_r;
reg [$clog2(SIZE)-1:0] rd_next_ptr_r;
reg empty_r;
reg full_r;
reg bypass_r;
always @(posedge clk) begin
if (reset) begin
wr_ctr_r <= 0;
@@ -99,9 +111,10 @@ module VX_generic_queue_ll
always @(posedge clk) begin
if (reset) begin
rd_ptr_r <= 0;
curr_r <= 0;
rd_ptr_r <= 0;
rd_next_ptr_r <= 1;
bypass_r <= 0;
bypass_r <= 0;
end else begin
if (reading) begin
if (SIZE == 2) begin
@@ -123,7 +136,6 @@ module VX_generic_queue_ll
assign empty = empty_r;
assign full = full_r;
end
end
/* verilator lint_on WIDTH */