felsabbagh3
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1b7f28273b
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Removed -O3 from makefile
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2019-10-27 20:34:32 -04:00 |
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felsabbagh3
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0ee74bc566
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migrated 100% to modelsim
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2019-10-27 20:08:44 -04:00 |
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felsabbagh3
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715982cca7
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Modelsim Working + Simulating + dumping - Some bugs
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2019-10-27 03:36:02 -04:00 |
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felsabbagh3
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372c81d90c
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Generate VCD with ModelSim
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2019-10-26 19:35:21 -04:00 |
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felsabbagh3
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6fda88b68f
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Modelsim Makefile compile + simulate - DPI
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2019-10-26 19:01:49 -04:00 |
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felsabbagh3
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ad46194d1b
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fixed width
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2019-10-26 00:39:27 -04:00 |
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felsabbagh3
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1181af1df2
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Modelsim basic sim
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2019-10-26 00:34:57 -04:00 |
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Elsabbagh
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9110e8367e
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modelsim
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2019-10-25 23:41:34 -04:00 |
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felsabbagh3
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667dbfbbe8
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Trying icarus
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2019-10-25 22:54:02 -04:00 |
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felsabbagh3
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820007ae80
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NUM_REQ
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2019-10-25 13:46:31 -04:00 |
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felsabbagh3
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c85c01e082
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Parametized cache
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2019-10-25 13:36:06 -04:00 |
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felsabbagh3
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89d0390965
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CACHE FINALLY WORKING
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2019-10-25 04:01:23 -04:00 |
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felsabbagh3
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01efe02e8b
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CACHE WORKING just needs lb/sb
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2019-10-25 03:03:09 -04:00 |
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felsabbagh3
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1e648c5819
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FIxed first circular issue
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2019-10-24 10:38:04 -04:00 |
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felsabbagh3
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de8de00f6e
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Finished cache not tested
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2019-10-23 19:07:26 -04:00 |
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felsabbagh3
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6340ffcc2a
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new cache states
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2019-10-23 15:07:14 -04:00 |
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felsabbagh3
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1645a04b1d
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Fixed SM + added def SYN
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2019-10-22 15:56:30 -04:00 |
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felsabbagh3
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9d8273afe4
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Finished Cache Integration
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2019-10-22 06:02:08 -04:00 |
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felsabbagh3
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b7af8c3f34
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Integrated Shared Memory
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2019-10-22 05:03:47 -04:00 |
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felsabbagh3
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1bfafca896
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Cleanup before integration
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2019-10-22 03:03:17 -04:00 |
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felsabbagh3
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b3f464dd89
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Barriers impl + tested
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2019-10-22 01:47:39 -04:00 |
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felsabbagh3
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31d3d51392
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WSPAWN imp + tested
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2019-10-21 23:35:53 -04:00 |
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felsabbagh3
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c21e400f9f
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Readded IPDOM stack + SPLIT/Join tested
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2019-10-21 21:26:21 -04:00 |
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felsabbagh3
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b6375e76de
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Readded IPDOM stack + SPLIT/Join tested
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2019-10-21 21:24:49 -04:00 |
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Lingjun Zhu
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e2cd8102eb
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Uncommented the necessary line about write_bit_mask on VX_gpr.v again, try synthesizing
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2019-10-21 17:09:51 -04:00 |
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felsabbagh3
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0672389edc
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fix
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2019-10-21 12:16:17 -04:00 |
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felsabbagh3
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ce49e2f223
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proper init warp scheduelr
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2019-10-21 12:13:34 -04:00 |
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felsabbagh3
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8050419511
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added begin
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2019-10-21 12:06:10 -04:00 |
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felsabbagh3
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85004899bd
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added reset to ws
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2019-10-21 12:03:07 -04:00 |
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felsabbagh3
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99586279d9
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always fix stack
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2019-10-21 11:49:10 -04:00 |
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felsabbagh3
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292c792339
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generic stack reset
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2019-10-21 11:45:51 -04:00 |
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felsabbagh3
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4bfdbb5188
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reset posedge
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2019-10-21 11:34:12 -04:00 |
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felsabbagh3
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49b139d512
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fix
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2019-10-21 11:24:45 -04:00 |
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felsabbagh3
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121a985d12
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Reset to Generic Register
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2019-10-21 11:21:13 -04:00 |
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felsabbagh3
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bab1852a99
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Added Split/Join - not tested
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2019-10-21 03:03:15 -04:00 |
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felsabbagh3
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84f5ccb484
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Added CSR TID/WID reads
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2019-10-21 02:10:05 -04:00 |
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felsabbagh3
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797801ebae
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CENA/CENB Modifications + Still not working
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2019-10-19 14:52:57 -04:00 |
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felsabbagh3
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4cae140ac1
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Mem technology compiling but still reading all zeros
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2019-10-18 16:45:42 -04:00 |
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felsabbagh3
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f7d826593f
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TMC working and tested
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2019-10-18 16:09:06 -04:00 |
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felsabbagh3
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f7b55427b4
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Added ISA2 infrastructure with bugs
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2019-10-18 05:21:32 -04:00 |
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felsabbagh3
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629ed3f8f9
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Before ISA2.0
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2019-10-18 04:15:34 -04:00 |
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felsabbagh3
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559c64cb36
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Cleanup
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2019-10-18 02:20:38 -04:00 |
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felsabbagh3
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505bbc20c8
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Removed FWD
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2019-10-18 02:01:39 -04:00 |
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felsabbagh3
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6b729fd2ea
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minor
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2019-10-18 01:46:38 -04:00 |
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felsabbagh3
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ccbb2acab5
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LSU+EXU minor
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2019-10-17 22:38:09 -04:00 |
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felsabbagh3
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6779d0fade
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Instruction Multiplex LSU/EXU 1 cycle DONE
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2019-10-17 22:29:21 -04:00 |
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Lingjun Zhu
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a4d6ada16d
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Fixed the issues of memory during synthesis
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2019-10-17 14:18:52 -04:00 |
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felsabbagh3
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9bf186fc77
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minor
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2019-10-17 11:51:11 -04:00 |
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felsabbagh3
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e8a43fa7a9
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minor
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2019-10-17 11:44:19 -04:00 |
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felsabbagh3
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10fbb53c38
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minor
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2019-10-17 11:29:40 -04:00 |
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