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CACHE WORKING just needs lb/sb

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This commit is contained in:
felsabbagh3
2019-10-25 03:03:09 -04:00
parent 1e648c5819
commit 01efe02e8b
19 changed files with 2302 additions and 2358 deletions
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8
rtl/Makefile
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@@ -11,11 +11,11 @@ EXE=--exe ./simulate/test_bench.cpp
COMP=--compiler gcc
# WNO=-Wno-UNDRIVEN --Wno-PINMISSING -Wno-STMTDLY -Wno-WIDTH -Wno-UNSIGNED
WNO=
WNO=-Wno-UNDRIVEN --Wno-PINMISSING -Wno-STMTDLY -Wno-WIDTH -Wno-UNSIGNED -Wno-UNOPTFLAT
# WNO=
LIGHTW=
# LIGHTW=-Wno-UNOPTFLAT
# LIGHTW=
LIGHTW=-Wno-UNOPTFLAT
# LIB=-LDFLAGS '-L/usr/local/systemc/'
LIB=

7
rtl/VX_back_end.v
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@@ -31,6 +31,7 @@ assign VX_writeback_inter.wb_warp_num = VX_writeback_temp.wb_warp_num;
VX_mw_wb_inter VX_mw_wb();
wire no_slot_mem;
VX_mem_req_inter VX_exe_mem_req();
@@ -78,7 +79,8 @@ VX_lsu load_store_unit(
.VX_mem_wb (VX_mem_wb),
.VX_dcache_rsp(VX_dcache_rsp),
.VX_dcache_req(VX_dcache_req),
.out_delay (out_mem_delay)
.out_delay (out_mem_delay),
.no_slot_mem (no_slot_mem)
);
@@ -106,7 +108,8 @@ VX_writeback VX_wb(
.VX_inst_exec_wb (VX_inst_exec_wb),
.VX_csr_wb (VX_csr_wb),
.VX_writeback_inter(VX_writeback_temp)
.VX_writeback_inter(VX_writeback_temp),
.no_slot_mem (no_slot_mem)
);
endmodule

7
rtl/VX_dmem_controller.v
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@@ -22,8 +22,8 @@ module VX_dmem_controller (
wire[`NT_M1:0][31:0] cache_driver_in_address = VX_dcache_req.out_cache_driver_in_address;
wire[2:0] cache_driver_in_mem_read = VX_dcache_req.out_cache_driver_in_mem_read;
wire[2:0] cache_driver_in_mem_write = VX_dcache_req.out_cache_driver_in_mem_write;
wire[2:0] cache_driver_in_mem_read = !(|cache_driver_in_valid) ? `NO_MEM_READ : VX_dcache_req.out_cache_driver_in_mem_read;
wire[2:0] cache_driver_in_mem_write = !(|cache_driver_in_valid) ? `NO_MEM_WRITE : VX_dcache_req.out_cache_driver_in_mem_write;
wire[`NT_M1:0][31:0] cache_driver_in_data = VX_dcache_req.out_cache_driver_in_data;
@@ -34,6 +34,9 @@ module VX_dmem_controller (
wire cache_delay;
wire valid_read_cache = !cache_delay && cache_driver_in_valid[0];
VX_shared_memory #(.NB(7), .BITS_PER_BANK(3)) shared_memory (
.clk (clk),
.in_valid (sm_driver_in_valid),

35
rtl/VX_lsu.v
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@@ -5,6 +5,7 @@
module VX_lsu (
input wire clk,
input wire reset,
input wire no_slot_mem,
VX_lsu_req_inter VX_lsu_req,
// Write back to GPR
@@ -15,9 +16,9 @@ module VX_lsu (
output wire out_delay
);
VX_inst_mem_wb_inter VX_mem_wb_temp();
// VX_inst_mem_wb_inter VX_mem_wb_temp();
assign out_delay = VX_dcache_rsp.delay;
assign out_delay = VX_dcache_rsp.delay || no_slot_mem;
// Generate Addresses
@@ -36,30 +37,30 @@ module VX_lsu (
assign VX_dcache_req.out_cache_driver_in_data[index] = VX_lsu_req.store_data[index];
assign VX_dcache_req.out_cache_driver_in_valid[index] = (VX_lsu_req.valid[index]);
assign VX_mem_wb_temp.loaded_data[index] = VX_dcache_rsp.in_cache_driver_out_data[index];
assign VX_mem_wb.loaded_data[index] = VX_dcache_rsp.in_cache_driver_out_data[index];
end
assign VX_dcache_req.out_cache_driver_in_mem_read = VX_lsu_req.mem_read;
assign VX_dcache_req.out_cache_driver_in_mem_write = VX_lsu_req.mem_write;
assign VX_mem_wb_temp.rd = VX_lsu_req.rd;
assign VX_mem_wb_temp.wb = VX_lsu_req.wb;
assign VX_mem_wb_temp.wb_valid = VX_lsu_req.valid;
assign VX_mem_wb_temp.wb_warp_num = VX_lsu_req.warp_num;
assign VX_mem_wb.rd = VX_lsu_req.rd;
assign VX_mem_wb.wb = VX_lsu_req.wb & {!VX_dcache_rsp.delay, !VX_dcache_rsp.delay};
assign VX_mem_wb.wb_valid = VX_lsu_req.valid;
assign VX_mem_wb.wb_warp_num = VX_lsu_req.warp_num;
wire zero_temp = 0;
VX_generic_register #(.N(142)) register_wb_data
(
.clk (clk),
.reset(reset),
.stall(zero_temp),
.flush(out_delay),
.in ({VX_mem_wb_temp.loaded_data, VX_mem_wb_temp.rd, VX_mem_wb_temp.wb, VX_mem_wb_temp.wb_valid, VX_mem_wb_temp.wb_warp_num}),
.out ({VX_mem_wb.loaded_data , VX_mem_wb.rd , VX_mem_wb.wb , VX_mem_wb.wb_valid , VX_mem_wb.wb_warp_num })
);
// wire zero_temp = 0;
// VX_generic_register #(.N(142)) register_wb_data
// (
// .clk (clk),
// .reset(reset),
// .stall(zero_temp),
// .flush(out_delay),
// .in ({VX_mem_wb_temp.loaded_data, VX_mem_wb_temp.rd, VX_mem_wb_temp.wb, VX_mem_wb_temp.wb_valid, VX_mem_wb_temp.wb_warp_num}),
// .out ({VX_mem_wb.loaded_data , VX_mem_wb.rd , VX_mem_wb.wb , VX_mem_wb.wb_valid , VX_mem_wb.wb_warp_num })
// );
endmodule // Memory

7
rtl/VX_priority_encoder_w_mask.v
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@@ -13,13 +13,16 @@ module VX_priority_encoder_w_mask
always @(valids) begin
index = 0;
found = 0;
mask = 0;
// mask = 0;
for (i = 0; i < N; i=i+1) begin
if (valids[i]) begin
index = i[$clog2(N)-1:0];
found = 1;
mask[i[$clog2(N)-1:0]] = 1 << i;
// mask[index] = (1 << i);
// $display("%h",(1 << i));
end
end
end
assign mask = found ? (1 << index) : 0;
endmodule

16
rtl/VX_writeback.v
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@@ -11,10 +11,12 @@ module VX_writeback (
VX_csr_wb_inter VX_csr_wb,
// Actual WB to GPR
VX_wb_inter VX_writeback_inter
VX_wb_inter VX_writeback_inter,
output wire no_slot_mem
);
assign no_slot_mem = mem_wb && (exec_wb || csr_wb);
wire exec_wb = (VX_inst_exec_wb.wb != 0) && (|VX_inst_exec_wb.wb_valid);
wire mem_wb = (VX_mem_wb.wb != 0) && (|VX_mem_wb.wb_valid);
@@ -22,29 +24,29 @@ module VX_writeback (
assign VX_writeback_inter.write_data = exec_wb ? VX_inst_exec_wb.alu_result :
mem_wb ? VX_mem_wb.loaded_data :
csr_wb ? VX_csr_wb.csr_result :
mem_wb ? VX_mem_wb.loaded_data :
0;
assign VX_writeback_inter.wb_valid = exec_wb ? VX_inst_exec_wb.wb_valid :
mem_wb ? VX_mem_wb.wb_valid :
csr_wb ? VX_csr_wb.valid :
0;
mem_wb ? VX_mem_wb.wb_valid :
0;
assign VX_writeback_inter.rd = exec_wb ? VX_inst_exec_wb.rd :
mem_wb ? VX_mem_wb.rd :
csr_wb ? VX_csr_wb.rd :
mem_wb ? VX_mem_wb.rd :
0;
assign VX_writeback_inter.wb = exec_wb ? VX_inst_exec_wb.wb :
mem_wb ? VX_mem_wb.wb :
csr_wb ? VX_csr_wb.wb :
mem_wb ? VX_mem_wb.wb :
0;
assign VX_writeback_inter.wb_warp_num = exec_wb ? VX_inst_exec_wb.wb_warp_num :
mem_wb ? VX_mem_wb.wb_warp_num :
csr_wb ? VX_csr_wb.warp_num :
mem_wb ? VX_mem_wb.wb_warp_num :
0;

19
rtl/Vortex.v
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@@ -7,6 +7,9 @@ module Vortex(
input wire reset,
input wire[31:0] icache_response_instruction,
output wire[31:0] icache_request_pc_address,
// IO
output wire io_valid,
output wire[31:0] io_data,
// Req
output reg [31:0] o_m_read_addr,
output reg [31:0] o_m_evict_addr,
@@ -20,11 +23,20 @@ module Vortex(
output wire out_ebreak
);
// Dcache Interface
wire memory_delay;
wire gpr_stage_delay;
wire schedule_delay;
// Dcache Interface
VX_dcache_response_inter VX_dcache_rsp();
VX_dcache_request_inter VX_dcache_req();
wire temp_io_valid = (!memory_delay) && (|VX_dcache_req.out_cache_driver_in_valid) && (VX_dcache_req.out_cache_driver_in_mem_write != `NO_MEM_WRITE) && (VX_dcache_req.out_cache_driver_in_address[0] == 32'h00010000);
wire[31:0] temp_io_data = VX_dcache_req.out_cache_driver_in_data[0];
assign io_valid = temp_io_valid;
assign io_data = temp_io_data;
VX_dram_req_rsp_inter VX_dram_req_rsp();
@@ -74,11 +86,6 @@ VX_jal_response_inter VX_jal_rsp(); // Jump resolution to Fetch
VX_warp_ctl_inter VX_warp_ctl();
wire memory_delay;
wire gpr_stage_delay;
wire schedule_delay;
VX_front_end vx_front_end(
.clk (clk),
.reset (reset),

9
rtl/cache/VX_Cache_Bank.v vendored
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@@ -90,10 +90,10 @@ module VX_Cache_Bank
assign data_evicted = data_use;
assign eviction_wb = miss && (dirty_use != 1'b0);
assign eviction_wb = (dirty_use != 1'b0) && valid_use;
assign eviction_tag = tag_use;
assign access = (state == CACHE_IDLE) && valid_in;
assign write_from_mem = (state == RECIV_MEM_RSP) && valid_in;
assign write_from_mem = (state == RECIV_MEM_RSP);
assign readdata = (access) ? data_use[block_offset] : 32'b0; // Fix with actual data
assign hit = (access && (tag_use == o_tag) && valid_use);
//assign eviction_addr = {eviction_tag, actual_index, block_offset, 5'b0}; // Fix with actual data
@@ -104,9 +104,8 @@ module VX_Cache_Bank
wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] data_write;
genvar g;
for (g = 0; g < `NUM_WORDS_PER_BLOCK; g = g + 1) begin
wire correct_block = (block_offset == g);
assign we[g] = (read_or_write && ((access && correct_block) || (write_from_mem && !correct_block)) ) ? 1'b1 : 1'b0;
//assign we[g] = (!(write_from_mem && correct_block) && ((write_from_mem || correct_block) && read_or_write == 1'b1)) ? 1 : 0; // added the "not"
wire normal_write = (read_or_write && ((access && (block_offset == g))) && !miss);
assign we[g] = (normal_write || (write_from_mem)) ? 1'b1 : 1'b0;
assign data_write[g] = write_from_mem ? fetched_writedata[g] : writedata;
end

17
rtl/cache/VX_cache_bank_valid.v vendored
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@@ -7,17 +7,16 @@ module VX_cache_bank_valid
(
input wire [`NT_M1:0] i_p_valid,
input wire [`NT_M1:0][31:0] i_p_addr,
output wire [NUMBER_BANKS - 1 : 0][`NT_M1:0] thread_track_banks
output reg [NUMBER_BANKS - 1 : 0][`NT_M1:0] thread_track_banks
);
genvar t_id;
for (t_id = 0; t_id <= `NT_M1; t_id = t_id + 1)
begin
wire[2:0] threads_bank = i_p_addr[t_id][4:2];
assign thread_track_banks[threads_bank][t_id] = i_p_valid[t_id];
end
always @(*) begin
thread_track_banks = 0;
for (t_id = 0; t_id <= `NT_M1; t_id = t_id + 1)
begin
thread_track_banks[i_p_addr[t_id][4:2]][t_id] = i_p_valid[t_id];
end
end
endmodule

48
rtl/cache/VX_d_cache.v vendored
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@@ -64,9 +64,10 @@ module VX_d_cache(clk,
// Buffer for final data
reg [`NT_M1:0][31:0] final_data_read;
wire[`NT_M1:0][31:0] new_final_data_read;
reg [`NT_M1:0][31:0] new_final_data_read;
wire[`NT_M1:0][31:0] new_final_data_read_Qual;
assign o_p_readdata = final_data_read;
assign o_p_readdata = new_final_data_read_Qual;
@@ -95,6 +96,8 @@ module VX_d_cache(clk,
reg[31:0] miss_addr;
reg[31:0] evict_addr;
wire curr_processor_request_valid = (|i_p_valid);
assign use_valid = (stored_valid == 0) ? i_p_valid : stored_valid;
@@ -121,10 +124,15 @@ module VX_d_cache(clk,
// end
// end
reg[`NT_M1:0] debug_hit_per_bank_mask[NUMBER_BANKS-1:0];
genvar bid;
for (bid = 0; bid < NUMBER_BANKS; bid=bid+1)
begin
wire[`NT_M1:0] use_threads_track_banks = thread_track_banks[bid];
wire[`NT_M1:0] use_threads_track_banks = thread_track_banks[bid];
wire[$clog2(`NT)-1:0] use_thread_index = index_per_bank[bid];
wire use_write_final_data = hit_per_bank[bid];
wire[31:0] use_data_final_data = readdata_per_bank[bid];
VX_priority_encoder_w_mask #(.N(`NT)) choose_thread(
.valids(use_threads_track_banks),
.mask (use_mask_per_bank[bid]),
@@ -132,17 +140,20 @@ module VX_d_cache(clk,
.found (valid_per_bank[bid])
);
assign new_final_data_read[index_per_bank[bid]] = hit_per_bank[bid] ? readdata_per_bank[bid] : 0;
assign threads_serviced_per_bank[bid] = use_mask_per_bank[bid] & {`NT{hit_per_bank[bid]}};
always @(*) begin
if (use_write_final_data) new_final_data_read[use_thread_index] = use_data_final_data;
end
// assign new_final_data_read[use_thread_index] = use_write_final_data ? use_data_final_data : 0;
assign debug_hit_per_bank_mask[bid] = {`NT{hit_per_bank[bid]}};
assign threads_serviced_per_bank[bid] = use_mask_per_bank[bid] & debug_hit_per_bank_mask[bid];
end
// genvar tid;
assign threads_serviced_Qual = threads_serviced_per_bank[0] | threads_serviced_per_bank[1] | threads_serviced_per_bank[2] | threads_serviced_per_bank[3] | threads_serviced_per_bank[4] | threads_serviced_per_bank[5] | threads_serviced_per_bank[6] | threads_serviced_per_bank[7];
// for(tid = 0; tid )
wire[NUMBER_BANKS - 1 : 0] detect_bank_miss;
assign threads_serviced_Qual = threads_serviced_per_bank[0] | threads_serviced_per_bank[1] |
threads_serviced_per_bank[2] | threads_serviced_per_bank[3] |
threads_serviced_per_bank[4] | threads_serviced_per_bank[5] |
threads_serviced_per_bank[6] | threads_serviced_per_bank[7];
// genvar bbid;
// always @(*) begin
// for (bbid = 0; bbid < NUMBER_BANKS; bbid=bbid+1)
@@ -152,6 +163,14 @@ module VX_d_cache(clk,
// end
genvar tid;
for (tid = 0; tid < `NT; tid =tid+1)
begin
assign new_final_data_read_Qual[tid] = threads_serviced_Qual[tid] ? new_final_data_read[tid] : final_data_read[tid];
end
assign detect_bank_miss = (valid_per_bank & ~hit_per_bank);
wire delay;
@@ -193,10 +212,7 @@ module VX_d_cache(clk,
evict_addr <= eviction_addr_per_bank[miss_bank_index];
end
for (cur_t = 0; cur_t < `NT; cur_t=cur_t+1)
begin
if (threads_serviced_Qual[cur_t]) final_data_read[cur_t] <= new_final_data_read[cur_t];
end
final_data_read <= new_final_data_read_Qual;
end
@@ -245,8 +261,8 @@ module VX_d_cache(clk,
// Mem Rsp
// Req to mem:
assign o_m_evict_addr = evict_addr;
assign o_m_read_addr = miss_addr;
assign o_m_evict_addr = evict_addr & 32'hffffffc0;
assign o_m_read_addr = miss_addr & 32'hffffffc0;
assign o_m_valid = (state == SEND_MEM_REQ);
assign o_m_read_or_write = (state == SEND_MEM_REQ) && (|eviction_wb);
//end

7
rtl/results.txt
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@@ -0,0 +1,7 @@
# Dynamic Instructions: 4139
# of total cycles: 4156
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.00411
# time to simulate: 6.95312e-310 milliseconds
# GRADE: Failed on test: 4294967295

2
rtl/simulate/test_bench.cpp
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@@ -5,7 +5,7 @@
int main(int argc, char **argv)
{
Verilated::debug(1);
// Verilated::debug(1);
Verilated::commandArgs(argc, argv);

248
rtl/simulate/test_bench.h
View File

@@ -39,6 +39,7 @@ class Vortex
void print_stats(bool = true);
bool ibus_driver();
bool dbus_driver();
void io_handler();
RAM ram;
@@ -188,77 +189,115 @@ bool Vortex::ibus_driver()
}
void Vortex::io_handler()
{
if (vortex->io_valid)
{
uint32_t data_write = (uint32_t) vortex->io_data;
char c = (char) data_write;
std::cerr << c;
}
}
bool Vortex::dbus_driver()
{
// printf("****************************\n");
vortex->i_m_ready = 0;
for (int i = 0; i < CACHE_NUM_BANKS; i++)
{
for (int j = 0; j < CACHE_WORDS_PER_BLOCK; j++)
{
vortex->i_m_readdata[i][j] = 0;
}
}
if (this->refill)
{
this->refill = false;
unsigned unordered_mem[32];
int num_iter = 0;
for (int i = 0; i < CACHE_WORDS_PER_BLOCK; i++)
{
for (int j = 0; j < (CACHE_NUM_BANKS*8); j+=8)
{
unsigned addr = this->refill_addr + (4*num_iter);
unsigned data_read;
ram.getWord(addr, &data_read);
unordered_mem[i+j] = data_read;
num_iter++;
}
}
vortex->i_m_ready = 1;
for (int i = 0; i < CACHE_NUM_BANKS; i++)
for (int curr_e = 0; curr_e < (CACHE_NUM_BANKS*CACHE_WORDS_PER_BLOCK); curr_e++)
{
for (int j = 0; j < CACHE_WORDS_PER_BLOCK; j++)
{
vortex->i_m_readdata[i][j] = unordered_mem[(i*CACHE_WORDS_PER_BLOCK)+j];
unsigned new_addr = this->refill_addr + (4*curr_e);
unsigned addr_without_byte = new_addr >> 2;
unsigned bank_num = addr_without_byte & 0x7;
unsigned addr_wihtout_bank = addr_without_byte >> 3;
unsigned offset_num = addr_wihtout_bank & 0x3;
unsigned value;
ram.getWord(new_addr, &value);
// printf("-------- (%x) i_m_readdata[%d][%d] (%d) = %d\n", new_addr, bank_num, offset_num, curr_e, value);
vortex->i_m_readdata[bank_num][offset_num] = value;
}
}
}
else
{
if (vortex->o_m_valid)
{
// printf("Valid o_m_valid\n");
if (vortex->o_m_read_or_write)
{
unsigned ordered_mem[32];
// printf("Valid write\n");
// Create unordered mem
unsigned unordered_mem[32];
for (int i = 0; i < CACHE_NUM_BANKS; i++)
for (int curr_e = 0; curr_e < (CACHE_NUM_BANKS*CACHE_WORDS_PER_BLOCK); curr_e++)
{
for (int j = 0; j < CACHE_WORDS_PER_BLOCK; j++)
{
unordered_mem[(i*CACHE_WORDS_PER_BLOCK)+j] = vortex->o_m_writedata[i][j];
}
unsigned new_addr = vortex->o_m_evict_addr + (4*curr_e);
unsigned addr_without_byte = new_addr >> 2;
unsigned bank_num = addr_without_byte & 0x7;
unsigned addr_wihtout_bank = addr_without_byte >> 3;
unsigned offset_num = addr_wihtout_bank & 0x3;
unsigned new_value = vortex->o_m_writedata[bank_num][offset_num];
ram.writeWord( new_addr, &new_value);
// printf("+++++++ (%x) writeback[%d][%d] (%d) = %d\n", new_addr, bank_num, offset_num, curr_e, new_value);
// printf("+++++++ (%x) i_m_readdata[%d][%d] (%d) = %d\n", new_addr, bank_num, offset_num, curr_e, value);
}
// Order the memory
int num_iter = 0;
for (int i = 0; i < CACHE_NUM_BANKS; i++)
{
for (int j = 0; j < (CACHE_NUM_BANKS*CACHE_WORDS_PER_BLOCK); j+=CACHE_WORDS_PER_BLOCK)
{
printf("i: %d, j: %d, num_iter: %d\n", i, j, num_iter);
ordered_mem[i+j] = unordered_mem[num_iter];
num_iter++;
}
}
// unsigned ordered_mem[32];
// Save the memory
for (int i = 0; i < (CACHE_WORDS_PER_BLOCK * CACHE_NUM_BANKS); i++)
{
unsigned addr = (vortex->o_m_evict_addr) + (4*i);
unsigned * data_addr = ordered_mem + i;
ram.writeWord( addr, data_addr);
}
// // Create unordered mem
// unsigned unordered_mem[32];
// for (int i = 0; i < CACHE_NUM_BANKS; i++)
// {
// for (int j = 0; j < CACHE_WORDS_PER_BLOCK; j++)
// {
// unordered_mem[(i*CACHE_WORDS_PER_BLOCK)+j] = vortex->o_m_writedata[i][j];
// }
// }
// // Order the memory
// int num_iter = 0;
// for (int i = 0; i < CACHE_NUM_BANKS; i++)
// {
// for (int j = 0; j < (CACHE_NUM_BANKS*CACHE_WORDS_PER_BLOCK); j+=CACHE_WORDS_PER_BLOCK)
// {
// printf("i: %d, j: %d, num_iter: %d\n", i, j, num_iter);
// ordered_mem[i+j] = unordered_mem[num_iter];
// num_iter++;
// }
// }
// // Save the memory
// for (int i = 0; i < (CACHE_WORDS_PER_BLOCK * CACHE_NUM_BANKS); i++)
// {
// unsigned addr = (vortex->o_m_evict_addr) + (4*i);
// unsigned * data_addr = ordered_mem + i;
// ram.writeWord( addr, data_addr);
// }
}
@@ -268,122 +307,6 @@ bool Vortex::dbus_driver()
}
}
// uint32_t data_read;
// uint32_t data_write;
// uint32_t addr;
// // std::cout << "DBUS DRIVER\n" << std::endl;
// ////////////////////// DBUS //////////////////////
// bool did = false;
// for (unsigned curr_th = 0; curr_th < NT; curr_th++)
// {
// if ((vortex->out_cache_driver_in_mem_write != NO_MEM_WRITE) && vortex->out_cache_driver_in_valid[curr_th])
// {
// did = true;
// data_write = (uint32_t) vortex->out_cache_driver_in_data[curr_th];
// addr = (uint32_t) vortex->out_cache_driver_in_address[curr_th];
// if (addr == 0x00010000)
// {
// std::cerr << (char) data_write;
// }
// // if ((addr >= 0x810002cc) && (addr < 0x810002d0))
// // {
// // int index = (addr - 0x810002cc) / 4;
// // // std::cerr << GREEN << "1done[" << index << "] = " << data_write << DEFAULT << "\n";
// // }
// // if ((addr >= 0x810059f4) && (addr < 0x810059f4))
// // {
// // int index = (addr - 0x810059f4) / 4;
// // // std::cerr << RED << "2done[" << index << "] = " << data_write << DEFAULT << "\n";
// // }
// if (vortex->out_cache_driver_in_mem_write == SB_MEM_WRITE)
// {
// data_write = ( data_write) & 0xFF;
// ram.writeByte( addr, &data_write);
// } else if (vortex->out_cache_driver_in_mem_write == SH_MEM_WRITE)
// {
// data_write = ( data_write) & 0xFFFF;
// ram.writeHalf( addr, &data_write);
// } else if (vortex->out_cache_driver_in_mem_write == SW_MEM_WRITE)
// {
// // printf("STORING %x in %x \n", data_write, addr);
// data_write = data_write;
// ram.writeWord( addr, &data_write);
// }
// }
// }
// // printf("----\n");
// for (unsigned curr_th = 0; curr_th < NT; curr_th++)
// {
// if ((vortex->out_cache_driver_in_mem_read != NO_MEM_READ) && vortex->out_cache_driver_in_valid[curr_th])
// {
// did = true;
// addr = (uint32_t) vortex->out_cache_driver_in_address[curr_th];
// ram.getWord(addr, &data_read);
// if (vortex->out_cache_driver_in_mem_read == LB_MEM_READ)
// {
// vortex->in_cache_driver_out_data[curr_th] = (data_read & 0x80) ? (data_read | 0xFFFFFF00) : (data_read & 0xFF);
// } else if (vortex->out_cache_driver_in_mem_read == LH_MEM_READ)
// {
// vortex->in_cache_driver_out_data[curr_th] = (data_read & 0x8000) ? (data_read | 0xFFFF0000) : (data_read & 0xFFFF);
// } else if (vortex->out_cache_driver_in_mem_read == LW_MEM_READ)
// {
// // printf("Reading mem - Addr: %x = %x\n", addr, data_read);
// // std::cout << "READING - Addr: " << std::hex << addr << " = " << data_read << "\n";
// // std::cout << std::dec;
// vortex->in_cache_driver_out_data[curr_th] = data_read;
// } else if (vortex->out_cache_driver_in_mem_read == LBU_MEM_READ)
// {
// vortex->in_cache_driver_out_data[curr_th] = (data_read & 0xFF);
// } else if (vortex->out_cache_driver_in_mem_read == LHU_MEM_READ)
// {
// vortex->in_cache_driver_out_data[curr_th] = (data_read & 0xFFFF);
// }
// else
// {
// vortex->in_cache_driver_out_data[curr_th] = 0xbabebabe;
// }
// }
// else
// {
// vortex->in_cache_driver_out_data[curr_th] = 0xbabebabe;
// }
// }
// if (did && (NW > 1))
// {
// if (NW < NT)
// {
// this->stats_total_cycles += NT % (NW -1);
// }
// }
// printf("******\n");
return false;
}
@@ -465,9 +388,11 @@ bool Vortex::simulate(std::string file_to_simulate)
// unsigned cycles;
counter = 0;
this->stats_total_cycles = 12;
while (this->stop && ((counter < 2)))
while (this->stop && ((counter < 5)))
// while (this->stats_total_cycles < 10)
{
// printf("-------------------------\n");
// std::cout << "Counter: " << counter << "\n";
// if ((this->stats_total_cycles) % 5000 == 0) std::cout << "************* Cycle: " << (this->stats_total_cycles) << "\n";
// dstop = !dbus_driver();
@@ -478,6 +403,7 @@ bool Vortex::simulate(std::string file_to_simulate)
vortex->eval();
istop = ibus_driver();
dstop = !dbus_driver();
io_handler();
#ifdef VCD_OUTPUT
m_trace->dump((2*this->stats_total_cycles)+1);