Hansung Kim
e40b7f0b8b
Support receiving trace filename from VPI for loggers
...
Useful for testing with different memtraces without having to recompile
design. This worked before for the trace driver but not for trace
logger.
Usage: make CONFIG=MemtraceCoreConfig run-binary-debug BINARY=none \
EXTRA_SIM_FLAGS="+memtracefile=nvbit.vecadd.n100000.filter_sm0.lane4.broken.trace"
2023-05-28 22:15:32 -07:00
Vamber Yang
9ecace676c
Add useful error msg
2023-05-19 17:47:40 -07:00
Hansung Kim
1886aefcc1
Parameterize tracefile has_source from Config
2023-05-09 22:22:27 -07:00
Hansung Kim
54a3e3cf72
Initiate memtrace DPI only when trace_read_ready
...
This is required because otherwise we might overwrite into
the Verilog registers that contain a valid trace line that
was missed by downstream when it was not ready. Basically
whenever trace_read_cycle stalls, we also want to stall
__in_* registers.
2023-05-08 14:34:52 -07:00
Hansung Kim
6b97b77572
Revert SimMemTrace.v to use posedge clock
...
Doing function calls inside @(*) causes lint errors. Instead, remove
staging registers to eliminate 1 cycle latency between DPI call and
when output is visible to Chisel.
2023-05-08 00:14:48 -07:00
Hansung Kim
ba600db7e4
Backport SimMemTrace fix
2023-05-07 23:54:49 -07:00
Hansung Kim
c75eaaf727
Backport SimMemTrace
2023-05-07 18:38:26 -07:00
Hansung Kim
2d4cd542c1
Backport SimMemTrace: non-chronological trace error
2023-05-06 23:21:08 -07:00
Hansung Kim
e64cb7a282
Backport SimMemTrace: enable parsing source, report errors
2023-05-06 23:13:45 -07:00
Hansung Kim
caa5ebf943
Reformat MemTraceReader
2023-05-06 01:47:33 -07:00
Vamber Yang
8ccaf3864d
Support for more realistic MemTracer step2 (DONE), make Verilog Blackbox DPI output data immediately and make .cc file maintain pointer when downstream is not ready
2023-05-02 22:06:16 -07:00
Vamber Yang
be0fcbd23b
Support for more realistic MemTracer step 1, allow Chisel MemTracer to input read_cycle to Verilog blackbox
2023-05-02 14:01:19 -07:00
Hansung Kim
0c0a8ec553
SimMemTraceLogger: store handle in class
2023-04-23 11:27:06 -07:00
Hansung Kim
8a7e6f1391
Replace hardcoded trace widths with proper params
2023-04-21 18:20:16 -07:00
Hansung Kim
3f9f7a1d67
Generate proper AccessAck/AccessAckData from response queue
2023-04-21 16:14:52 -07:00
Hansung Kim
02ce969c67
Fix width mismatch for source logger
2023-04-17 18:52:38 -07:00
Hansung Kim
d4a51cfee5
Log source ID in the trace
2023-04-17 18:43:17 -07:00
Hansung Kim
41d520a991
Log both request and response in trace logger
...
Inside DPI code, have a vector of unique_ptrs that act as handles to multiple
different trace logger instances. Each logger instance is instantiated in a
single instance of the Verilog module, and multiple of these Verilog modules may
be instantiated in the Chisel module (see simReq and simResp in MemTraceLogger).
2023-04-17 18:10:13 -07:00
Hansung Kim
8978c2a812
trait HasTraceReq
2023-04-17 16:51:37 -07:00
Hansung Kim
f60602fc34
Write trace from logger in the same format as driver
2023-04-17 16:26:25 -07:00
Hansung Kim
282434eb7d
Basic C++ file IO for trace logger
2023-04-17 16:20:27 -07:00
Hansung Kim
8e763b512a
Relay full trace line info to DPI
2023-04-12 13:54:59 -07:00
Hansung Kim
1057ed59d3
Parse log2(size) from trace; set is_store from TL opcode
2023-04-11 18:23:50 -07:00
Hansung Kim
71f334bb22
Fix size parsing from memtrace
2023-04-11 17:36:45 -07:00
Hansung Kim
dca52ace0b
Fix verilog lint error
2023-04-10 20:37:26 -07:00
Hansung Kim
b53711965e
Connect TL edge data to SimMemTraceLogger
...
TODO: since TileLink rounds all address down to a multiple of its beat
size (8 in the current code), we can't directly compare the memory trace
input to its output. Need to take masks into account.
2023-04-10 20:24:27 -07:00
Hansung Kim
af29acdcda
Placeholder for MemTraceLogger C++ code
2023-04-09 14:53:02 -07:00
Vamber Yang
8e5254292b
Attach MemTracer to SBus , all physical addr hashed between 0X80000000->0X90000000
2023-04-05 23:43:22 -07:00
Hansung Kim
bdc32b765f
Accept memory trace filename from VCS plusargs
...
Now can use `EXTRA_SIM_FLAGS="+memtracefile=<tracefile>"` to simulate
with different trace files without recompiling.
2023-04-03 17:41:47 -07:00
Hansung Kim
9bfb813e1b
Thread -> Lane
...
"thread" is confusing, unify to lane when denoting a hardware SIMD lane
inside a single warp.
2023-03-09 22:09:21 -08:00
Vamber Yang
0de09daa05
MemTracer able to read and write according to trace file, also support thread_id skipping in trace file
2023-03-08 17:34:10 -08:00
Hansung Kim
41ecf6bc20
Squelch debug prints in SimMemTrace
2023-03-07 17:53:09 -08:00
Hansung Kim
db9be56191
Properly connect each lane to TL node
2023-03-05 00:18:29 -08:00
Hansung Kim
172ab51355
Fix formatting and unused warnings
2023-03-03 23:44:50 -08:00
Hansung Kim
5f55a7578f
Recover lost changes
2023-03-03 22:36:54 -08:00
Hansung Kim
dcb49f7683
Doc update
2023-03-03 21:22:56 -08:00
Hansung Kim
9025729c0e
Emit address in addition to cycle
2023-02-27 17:36:54 -08:00
Hansung Kim
0ebaed5f1b
Communicate trace cycle data from C++ to Chisel
2023-02-27 14:40:49 -08:00
Hansung Kim
72de4bca66
Initial parsing of memory trace file in C++
2023-02-27 13:47:30 -08:00
Hansung Kim
80e4b5c734
Set up simple DPI for trace-driven testing
2023-02-26 20:39:19 -08:00
