Hansung Kim
ec02a12220
Use DecoupledIO instead of explicit valid in TraceLine bundle
2024-01-21 17:50:00 -08:00
Hansung Kim
d56981a0b1
Fix io.finished of MemTraceDriver not waiting for inflight responses
2024-01-21 15:33:15 -08:00
Hansung Kim
e183606193
Write basic DPI mem fuzzer
2024-01-20 21:47:06 -08:00
Hansung Kim
6ff127eb51
Write faux memory fuzzer
2024-01-19 22:37:44 -08:00
Hansung Kim
9e7a8f4ef2
Add FuzzerTile
...
This tile is similar to TraceGenTile in rocket-chip, where each tile
contains a memtrace generator/fuzzer that drives the intra-tile
coalescer and the rest of the memory subsystem.
2024-01-19 22:05:21 -08:00
Hansung Kim
69bf554d0f
Split SimMem verilog constants to a .vh file
2024-01-19 18:25:03 -08:00
Hansung Kim
40ec2a276b
Remove unittest configs carried over from rocket-chip
2024-01-19 18:24:22 -08:00
Hansung Kim
737f24fd77
scalafmt
2024-01-19 15:16:37 -08:00
Hansung Kim
fec3d61dd6
Decrease imemSourceWidth to 4
2024-01-18 22:16:22 -08:00
Hansung Kim
0fd4d0a76f
Split IO for lookup and dealloc in InflightTable
...
The usage of `lookup` and `lookupSourceId` ports were being conflated in
terms of table lookup and dealloc. Now `lookupSourceId` solely controls
lookup operation and vice versa. This simplifies pipeline reg logic in
uncoalescer.
2024-01-18 22:10:06 -08:00
Hansung Kim
9ae1d9c392
Put a pipeline stage at uncoalescer
...
... to cut timing after inflight table lookup & before
splitting/enqueueing logic.
2024-01-18 21:34:02 -08:00
Hansung Kim
7e906a39fb
Reduce default respQueueDepth to 2
2024-01-18 19:22:59 -08:00
Hansung Kim
95dcecbe03
Fix uncoalesced response being dropped
...
Need to use fire instead of valid so that the uncoalescing /
inflighttable freeing logic happens exactly once at the fire time.
FIXME: might result in long ready chain that goes from TL-D port all the
way to the response queues.
2024-01-18 18:50:43 -08:00
Hansung Kim
b1a37d0dda
Streamline upstream flow with regards to CoalSourceGen
...
CoalescerSourceGen was prematurely reclaiming sourceIds in the presence
of coalResp backpressure, since it was not referring to coalResp.fire
and instead setting ready to always-true. With this change
CoalSourceGen properly propagates both downstream and upstream
backpressure.
2024-01-18 18:15:18 -08:00
Hansung Kim
086b2a5398
Clean up uncoalescer -> respQueue doc
2024-01-18 18:12:49 -08:00
Hansung Kim
46f5e8b920
Disable force assert for RespQueue block
2024-01-18 18:10:33 -08:00
Hansung Kim
2b8ef4cb30
Create coalResp backpressure when response queues are full
...
... which causes the uncoalescer to lock up, so we shouldn't accept
further coalescer responses.
2024-01-18 01:09:28 -08:00
Hansung Kim
eeb92da8a1
Fix InFlightTable lookup assert
2024-01-18 01:07:49 -08:00
Hansung Kim
e96836c190
Fix inflightCounter debug counter
2024-01-18 01:06:28 -08:00
Hansung Kim
138e83b68a
Assert coreWriteReqQueue is never full in VortexCache
2024-01-18 01:05:23 -08:00
Hansung Kim
7914607304
Bump vortex with IBUF/LSUQ size change
2024-01-16 23:54:39 -08:00
Hansung Kim
37d2af5478
Reflect upstream rocket-chip changes
...
* hartId -> tileId
* TileCrossingParamsLike -> HierarchicalElementCrossingParamsLike
* don't use bus_error_unit
2024-01-16 23:44:57 -08:00
Hansung Kim
cd1022c608
Remove use of HasTiles to reflect upstream change
2024-01-16 22:59:56 -08:00
Hansung Kim
132742ea88
Distinguish LSU lanes from SIMD lanes and elaborate tag width logic
2024-01-16 22:20:16 -08:00
Richard Yan
dea005a179
incorporate vortex2
2024-01-16 17:41:33 -08:00
Richard Yan
f9b7e9fbe4
restructure from rocket-chip to radiance
2024-01-16 16:21:50 -08:00
Richard Yan
c742a13c1e
restructure: initial filter pass
2024-01-11 10:08:43 -08:00
Zekai Lin
ca57c8d6a3
TLFragmenter bug fix
2023-12-09 20:27:13 -08:00
Hansung Kim
0768a7abc9
More cleanup and doc
2023-11-10 18:49:11 -08:00
Hansung Kim
0bb8e6d705
Bump vortex with ibuffer size fix
2023-11-10 18:38:59 -08:00
Hansung Kim
ecfa18ce69
Rename to VortexBank
2023-11-10 17:46:04 -08:00
Hansung Kim
78e09160a2
Rename L1System -> VortexL1; do not expose bank Xbar from L1
2023-11-10 16:11:43 -08:00
Hansung Kim
257232dec8
Require MSHR size matches nSrcId to L2
2023-11-10 15:04:32 -08:00
Hansung Kim
5adf334af4
Scalafmt & rename & update doc
2023-11-10 14:58:16 -08:00
Hansung Kim
d51ce4cfa8
Reformat
2023-11-10 14:46:33 -08:00
Hansung Kim
17a39a369f
Cleanup conditional L1 instantiation
2023-11-10 14:42:33 -08:00
Hansung Kim
a0c15b2cc3
Use separate {imem,dmem}SourceWidth to fix deadlock
...
imemSourceWidth cannot be larger than the ibuffer size.
2023-11-08 20:20:17 -08:00
Hansung Kim
2f205be702
Update docs
2023-11-08 14:03:14 -08:00
Hansung Kim
571d33a5de
Remove unused MSB offset code from get getCoalescedDataChunk
2023-11-08 14:03:14 -08:00
Vamber Yang
61aad0315c
L1 FatBank Integration, multi-bank working with 4 dcache banks, 1 icache bank
...
Merge remote-tracking branch 'remotes/origin/graphics' into local-graphics-dev
2023-11-06 21:56:11 -08:00
Vamber Yang
e958ede277
multi-bank working when nBanks=2, encountered a putPartial error, need to pull latest change
2023-11-06 20:51:23 -08:00
Vamber Yang
be5134cd8a
L1 fatbank works with 2^5 source bits in SourceGen, failed with < 2^4 source bits in SourceGen
2023-11-01 23:48:24 -07:00
Hansung Kim
d2bfc31592
Fix store opcode assertion in AOpcodeIsStore
...
Now we support PutPartialData for narrow write requests that doesn't have all-1
mask.
2023-10-31 23:06:35 -07:00
Vamber Yang
75adb1dc66
Intergation of L1 Fatbank
2023-10-31 16:14:34 -07:00
Hansung Kim
635f4e42ff
Add detailed doc on source allocation/filtering
2023-10-25 20:55:01 -07:00
Hansung Kim
6371cdc03c
Use edge.hasData instead of TLUtils in adapter
2023-10-25 20:28:01 -07:00
Hansung Kim
1e8cc5ef90
Bump vortex
2023-10-25 20:07:20 -07:00
Hansung Kim
d70cbc8e58
Do matchingSources filtering using Vortex tag instead of TL source
...
Since we do source generation independently for each lane, if we use TL
source for filtering, it becomes possible that lane 0's source happens
to match lane 1/2/3's source even when they don't belong to the same
warp. Since Vortex uses dcache req ID that is unique across
instructions, using that for filtering prevents this bug. A better
solution would be to do source generation for all lanes at a time
though.
2023-10-25 19:48:21 -07:00
Hansung Kim
78e193db42
Add safety assert on sourceWidth
...
See commit 0d92eb65
2023-10-25 18:17:03 -07:00
Hansung Kim
09f512fda7
Don't reply write requests from Vortex core
2023-10-25 13:08:18 -07:00
