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623 Commits

Author SHA1 Message Date
Hansung Kim
abecd30b2b Store sourceId for every old req entry in table 2023-04-07 14:50:40 -07:00
Vamber Yang
8e5254292b Attach MemTracer to SBus , all physical addr hashed between 0X80000000->0X90000000 2023-04-05 23:43:22 -07:00
Hansung Kim
bdc32b765f Accept memory trace filename from VCS plusargs 
Now can use `EXTRA_SIM_FLAGS="+memtracefile=<tracefile>"` to simulate
with different trace files without recompiling.
 2023-04-03 17:41:47 -07:00
Hansung Kim
c0d502960f Experiment with coalescing across all lanes 2023-04-02 12:23:28 -07:00
Hansung Kim
d62732fb89 Invalidate outgoing per-lane requests that got coalesced 
Now the response queue no longer blocks the flow!
 2023-04-01 14:33:46 -07:00
Hansung Kim
d9f6e27a04 Move coalescer chiseltest to its own package 2023-03-31 20:51:34 -07:00
Hansung Kim
4aabbecda1 Do not deassert deq.valid right after invalidate(head) 
... to avoid combinational cycle.
 2023-03-31 20:40:12 -07:00
Hansung Kim
1c0c8fa112 Complete test for enqueuing to invalidated tail 2023-03-31 20:15:49 -07:00
Hansung Kim
92ad5c2548 Cleanup padding logic 2023-03-31 20:12:43 -07:00
Hansung Kim
3ee639f376 Eliminate unnecessary delay when invalidating head 
When invalidate signal is given for queue head, that head should be
gone immediately at the next cycle, regardless of what deq.ready was
at the previous cycle.
 2023-03-31 19:55:36 -07:00
Hansung Kim
6ca22a39e0 Implement automatic dequeuing of invalid entries 2023-03-31 19:40:10 -07:00
Hansung Kim
f44dfc8d5a Implement invalidation for the queue 2023-03-31 19:25:45 -07:00
Hansung Kim
a0d75530cb Use used mask in CoalShiftQueue 
Easier to use than wptr when enqueuing & dequeueing at the same time.
 2023-03-31 17:10:09 -07:00
Hansung Kim
303c43a5e2 Make CoalShiftQueue use wptr; add unit test 
Cannot solely rely on valid mask because there may be holes in the
middle.
 2023-03-29 19:06:08 -07:00
Hansung Kim
a3472752bf Duplicate ShiftQueue definition to make entries visible 2023-03-29 16:06:14 -07:00
Hansung Kim
12b3b67687 Store multiple oldSrcId reqs per lane in a table row 
The number of the per-lane reqs is controlled by `numPerLaneReqs`
rather than being set to 2 ** sourceWidth to allow some flexibility.
 2023-03-29 14:02:41 -07:00
Hansung Kim
3b335bda18 Basic unit test for the uncoalescer 2023-03-29 00:50:13 -07:00
Hansung Kim
9bc8f0074b Make uncoalescer a separate module for better testability 2023-03-28 17:07:54 -07:00
Hansung Kim
23d8fa3be1 Write simple test for MultiPortQueue 
... and comment out old CAM-based inflight table test.
 2023-03-27 15:21:01 -07:00
Hansung Kim
434013f816 Remove redundant coal edge handling code 2023-03-27 14:37:08 -07:00
Hansung Kim
d951de7810 Handle taking offset chunks in uncoalescing logic 
TODO: handling different size enums. Currently assumes everything is
4 bytes.
 2023-03-27 14:22:21 -07:00
Hansung Kim
4daa0cefd8 Check for response queue blocking 2023-03-27 02:18:30 -07:00
Hansung Kim
d745792d42 Use rocket-chip MultiPortQueue to serialize responses 
NOT tested yet
 2023-03-27 01:47:45 -07:00
Hansung Kim
0660923eb8 Split out CoalescingUnitImp 2023-03-27 01:12:28 -07:00
Hansung Kim
2416275e12 Enqueue some uncoalesced data to response queue 2023-03-27 00:58:03 -07:00
Hansung Kim
683a0172d8 Fix sourceWidth being wrongly taken from coalescer edge 2023-03-26 02:32:59 -07:00
Hansung Kim
a06911cf5b Make response queue, debug print for inflight entry 2023-03-26 01:07:53 -07:00
Hansung Kim
356aa9079f Make table RAM, not CAM 2023-03-23 21:16:05 -07:00
Hansung Kim
9f5b77145b Change inflight table entry to per-lane and per-srcId 2023-03-19 02:08:17 -07:00
Hansung Kim
08ce7dc57d Doc cleanup 2023-03-19 01:17:11 -07:00
Hansung Kim
2e06898dc0 Handle enqueue and lookup at the same cycle 
This fixes the inflight table filling up to full after some time in the
memtrace simulation.
 2023-03-13 16:22:22 -07:00
Hansung Kim
cb8ca183d5 Add debug counter for per-lane inflight reqs 2023-03-13 15:37:52 -07:00
Hansung Kim
400b356cfb Fix lookup succeeding on invalid entry; add test case 
also enable VCS FSDB annotation in chiseltest
 2023-03-12 03:26:09 -07:00
Hansung Kim
6de95587de Add chiseltest for inflight table 2023-03-11 23:20:50 -08:00
Hansung Kim
df0c2ba89f Flip lookup signal flow 
'ready' is now an input port that an external module uses to initiate
lookup, and 'valid' and 'bits' send the match result and table entry
back to the outside.  So far that's similar to a dequeue, but since we
also need to receive a sourceId key for the lookup, make a new input
port alongside the r/v interface.  Feels a little hacky but works for
now.
 2023-03-10 19:15:08 -08:00
Hansung Kim
2ba03fc16d Write sourceId lookup logic for table 2023-03-10 18:32:15 -08:00
Hansung Kim
3887129994 Write enqueue and reset logic for table 2023-03-10 18:00:38 -08:00
Hansung Kim
9256b8f6a3 Write simple next-empty-entry finding logic 2023-03-10 17:27:04 -08:00
Hansung Kim
6866b537d6 Separate out InflightCoalReqTable into a module 2023-03-10 15:28:28 -08:00
Hansung Kim
da58ab552f Construct entry for in-flight coalesced requests table 2023-03-10 14:22:43 -08:00
Hansung Kim
93b198e0f6 Properly assert ready/valid for all TL channels 2023-03-10 00:22:38 -08:00
Hansung Kim
e523b4235a Make placeholder for inflight coalesced request table 2023-03-09 23:48:12 -08:00
Hansung Kim
13552593c8 Check legal from Get and Put 2023-03-09 22:56:34 -08:00
Hansung Kim
46d3109e82 Skip instantiating queue for the edge from master node 2023-03-09 22:39:49 -08:00
Hansung Kim
9bfb813e1b Thread -> Lane 
"thread" is confusing, unify to lane when denoting a hardware SIMD lane
inside a single warp.
 2023-03-09 22:09:21 -08:00
Hansung Kim
a495149869 Connect coal master node to identitynode internally 
Instead of exposing master node to downstream, wrap everything inside
the IdentityNode with N+1:N+1 edges. The inward edges exposed to the
upstream nodes are only N edges. Needs more testing.
 2023-03-09 20:53:52 -08:00
Hansung Kim
f0069ba3ad Set lgSize=0 as memtrace addresses are not aligned 
This is TODO, we need to have a logic inside MemTraceDriver that aligns
these addresses to word boundaries and sets the right masks, similar to
how an actual core issues load/stores.
 2023-03-09 20:50:34 -08:00
Hansung Kim
babbdf9550 Left out fromSource 2023-03-08 18:36:47 -08:00
Hansung Kim
70b715645c Parameterize sourceId width for reg entry 2023-03-08 18:32:06 -08:00
Hansung Kim
a2ceb8c628 Fix sourceId collision by using a counter 2023-03-08 18:31:03 -08:00