Construct entry for in-flight coalesced requests table
This commit is contained in:
Hansung Kim
@@ -6,18 +6,29 @@ import chisel3._
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import chisel3.util._
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.devices.tilelink.TLTestRAM
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// import freechips.rocketchip.devices.tilelink.TLTestRAM
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import freechips.rocketchip.util.ShiftQueue
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import freechips.rocketchip.unittest._
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class CoalRegEntry(val sourceWidth: Int, val addressWidth: Int) extends Bundle {
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val source = UInt(sourceWidth.W)
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val address = UInt(addressWidth.W)
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val data = UInt(64.W /* FIXME hardcoded */ )
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}
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class CoalescingUnit(numLanes: Int = 1)(implicit p: Parameters)
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extends LazyModule {
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// Describes uncoalesced memory request that originated from a single lane
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class UncoalReq(val sourceWidth: Int, val addressWidth: Int) extends Bundle {
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val source = UInt(sourceWidth.W)
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val address = UInt(addressWidth.W)
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val data = UInt(64.W /* FIXME hardcoded */ )
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}
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class InflightCoalReqTableEntry(val sourceWidth: Int) extends Bundle {
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// Bit flags that show which lanes got coalesced into this request
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val fromLane = UInt(numLanes.W)
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// sourceId of the original requests before getting coalesced. We need to
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// know this in order to respond to the original per-lane TL requests with
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// matching sourceIds
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val sourceIds = Vec(numLanes, UInt(sourceWidth.W))
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}
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// val beatBytes = 8
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// val seqParam = Seq(
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// TLSlaveParameters.v1(
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@@ -40,13 +51,17 @@ class CoalescingUnit(numLanes: Int = 1)(implicit p: Parameters)
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// upstream node will connect to.
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val node = TLIdentityNode()
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// Number of maximum in-flight coalesced requests. The upper bound of this
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// value would be the sourceId range of a single lane.
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val numInflightCoalRequests = 4
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// Master node that actually generates coalesced requests.
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// This and the IdentityNode will be the two outward-facing nodes that the
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// downstream, either L1 or the system bus, will connect to.
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protected val coalParam = Seq(
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TLMasterParameters.v1(
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name = "CoalescerNode",
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sourceId = IdRange(0, 0x10)
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sourceId = IdRange(0, numInflightCoalRequests)
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)
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)
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protected val coalescerNode = TLClientNode(
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@@ -62,7 +77,7 @@ class CoalescingUnit(numLanes: Int = 1)(implicit p: Parameters)
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// Instantiate per-lane queue that buffers incoming requests.
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val sourceWidth = node.in(0)._1.params.sourceBits
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val addressWidth = node.in(0)._1.params.addressBits
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val coalRegEntry = new CoalRegEntry(sourceWidth, addressWidth)
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val coalRegEntry = new UncoalReq(sourceWidth, addressWidth)
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val queues = Seq.tabulate(numLanes) { _ =>
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Module(
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new ShiftQueue(coalRegEntry, 4 /* FIXME hardcoded */ )
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@@ -114,31 +129,80 @@ class CoalescingUnit(numLanes: Int = 1)(implicit p: Parameters)
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// Generate coalesced requests
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// FIXME: currently generating bogus coalesced requests
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val coalSourceId = RegInit(0.U(4.W /* FIXME hardcoded */ ))
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val coalSourceId = RegInit(0.U(2.W /* FIXME hardcoded */ ))
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coalSourceId := coalSourceId + 1.U
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val (tlCoal, edgeCoal) = coalescerNode.out(0)
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tlCoal.a.valid := true.B
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val coalReqAddress = Wire(UInt(tlCoal.params.addressBits.W))
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// TODO: bogus address
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coalReqAddress := (0xabcd.U + coalSourceId) << 4
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val coalReqValid = Wire(Bool())
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coalReqValid := true.B
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val (legal, bits) = edgeCoal.Get(
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fromSource = coalSourceId,
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// `toAddress` should be aligned to 2**lgSize
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toAddress = (0xabcd.U + coalSourceId) << 4,
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toAddress = coalReqAddress,
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// 64 bits = 8 bytes = 2**(3) bytes
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lgSize = 3.U
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)
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assert(legal, "unhandled illegal TL req gen")
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tlCoal.a.valid := coalReqValid
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tlCoal.a.bits := bits
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tlCoal.b.ready := true.B
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tlCoal.c.valid := false.B
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tlCoal.d.ready := true.B
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tlCoal.e.valid := false.B
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// Debug signals
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val coalReqValid = Wire(Bool())
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coalReqValid := tlCoal.a.valid
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// Populate inflight coalesced request table for use in un-coalescing
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// responses back to the individual lanes that they originated from.
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val inflightCoalReqTableEntry = new InflightCoalReqTableEntry(sourceWidth)
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val inflightCoalReqTable = Module(
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new Queue(inflightCoalReqTableEntry, numInflightCoalRequests)
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)
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val tableEntry = Wire(inflightCoalReqTableEntry)
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// TODO: bogus fromLane
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tableEntry.fromLane := coalSourceId & ((2 << numLanes) - 1).U
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// FIXME: I'm positive this is not the right way to do this
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tableEntry.sourceIds(0) := 0.U
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tableEntry.sourceIds(1) := 0.U
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tableEntry.sourceIds(2) := 0.U
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tableEntry.sourceIds(3) := 0.U
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dontTouch(tableEntry)
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inflightCoalReqTable.io.enq.valid := coalReqValid
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inflightCoalReqTable.io.enq.bits := tableEntry
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inflightCoalReqTable.io.deq.ready := false.B
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dontTouch(inflightCoalReqTable.io.deq.valid)
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dontTouch(inflightCoalReqTable.io.deq.bits)
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// Now, for the coalescer response flow, instantiate a reservation
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// station-like structure that records for each unanswered coalesced
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// requests which lane the request originated from, what their original
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// sourceId were, etc.
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// FIXME: Reuse ShiftQueue(coalRegEntry) for now, but swap out to actual
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// table structure
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// val inflightCoalReqTable = Reg(
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// Vec(NumInflightCoalRequests, new InflightCoalReqEntry(sourceWidth))
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// )
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(node.in zip node.out)(0) match {
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case ((tlIn, edgeIn), (tlOut, _)) =>
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assert(
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edgeIn.master.masters(0).name == "CoalescerNode",
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"First edge is not connected to the coalescer master node"
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)
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tlOut.a <> tlIn.a
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// No need to drop any incoming coalesced responses, so just passthrough
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// to master node
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tlIn.d <> tlOut.d
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dontTouch(tlIn.d)
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dontTouch(tlOut.d)
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}
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// Debug
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dontTouch(coalReqValid)
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val coalReqAddress = Wire(UInt(tlCoal.params.addressBits.W))
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coalReqAddress := tlCoal.a.bits.address
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dontTouch(coalReqAddress)
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val coalRespData = Wire(UInt(tlCoal.params.dataBits.W))
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coalRespData := tlCoal.d.bits.data
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@@ -146,38 +210,6 @@ class CoalescingUnit(numLanes: Int = 1)(implicit p: Parameters)
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dontTouch(tlCoal.a)
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dontTouch(tlCoal.d)
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// Now, for the coalescer response flow, instantiate a reservation
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// station-like structure that records for each unanswered coalesced
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// requests which lane the request originated from, what were their
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// original sourceIds, etc.
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// FIXME: Reuse ShiftQueue(coalRegEntry) for now, but swap out to actual
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// table structure
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val responseQueue = Module(
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new ShiftQueue(coalRegEntry, 4 /* FIXME hardcoded */ )
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)
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(node.in zip node.out)(0) match {
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case ((tlIn, edgeIn), (tlOut, _)) =>
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assert(
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edgeIn.master.masters(0).name == "CoalescerNode",
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"First edge is not connected to the coalescer master node"
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)
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val resp = Wire(coalRegEntry)
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resp.source := tlOut.d.bits.source
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resp.address := 0.U
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resp.data := tlOut.d.bits.data
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responseQueue.io.enq.valid := tlOut.d.valid
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responseQueue.io.enq.bits := resp
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responseQueue.io.deq.ready := true.B
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dontTouch(responseQueue.io.deq.valid)
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dontTouch(responseQueue.io.deq.bits)
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tlIn.d.valid := false.B
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dontTouch(tlIn.d)
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dontTouch(tlOut.d)
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}
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}
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}
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