Richard Yan
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459c14bb62
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add testing infrastructure for coalescing unit
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2023-05-02 17:38:49 -07:00 |
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Vamber Yang
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be0fcbd23b
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Support for more realistic MemTracer step 1, allow Chisel MemTracer to input read_cycle to Verilog blackbox
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2023-05-02 14:01:19 -07:00 |
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Richard Yan
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b9953e43ca
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TL helper methods for entry types
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2023-05-02 01:39:27 -07:00 |
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Richard Yan
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997b421c42
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active byte lane implementation for multi coalescer & add one shift queue test
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2023-05-02 00:07:45 -07:00 |
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Richard Yan
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6757ea1bbd
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shift queue bug fixes + new unit test
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2023-05-01 00:51:31 -07:00 |
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Richard Yan
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224bc65bcc
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Merge branch 'graphics' of https://github.com/hansungk/rocket-chip into graphics
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2023-04-30 17:59:16 -07:00 |
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Richard Yan
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55b2f7c33f
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reworked shift queue
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2023-04-30 17:59:10 -07:00 |
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Hansung Kim
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03be55fd4e
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Alternative bogus logic for synthesis-only driver
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2023-04-29 22:34:12 -07:00 |
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Hansung Kim
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0270d82882
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Touch TL D data to save uncoalescer from synthesis opt-out
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2023-04-29 14:14:18 -07:00 |
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Hansung Kim
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81635d49db
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Add a dummy test target for use in synthesis
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2023-04-29 13:20:44 -07:00 |
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Richard Yan
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12d2912368
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Merge branch 'graphics' of https://github.com/hansungk/rocket-chip into graphics
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2023-04-28 20:51:08 -07:00 |
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Richard Yan
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c655874470
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width widget in DummyCoalescingUnitTB
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2023-04-28 20:47:47 -07:00 |
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Hansung Kim
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fec788d648
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Invalidate head when dequeued but allowShift was false
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2023-04-28 15:46:45 -07:00 |
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Hansung Kim
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a49931ae60
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Add invalidate/enq test case for depth=1 CoalShiftQueue
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2023-04-28 15:08:39 -07:00 |
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Hansung Kim
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44d3c09b6d
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Fix used bit logic when invalidating but not dequeueing
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2023-04-28 14:58:47 -07:00 |
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Hansung Kim
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2622bf04d3
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Add allowShift to CoalShiftQueue IO to synchronize shifting
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2023-04-28 14:12:51 -07:00 |
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Hansung Kim
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fc948b36d8
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Only compare leader against followers >= leader idx
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2023-04-28 01:37:36 -07:00 |
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Hansung Kim
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f12211b9cc
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Remove duplicate instantiation of table entryT
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2023-04-28 01:15:37 -07:00 |
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Hansung Kim
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f7bf277e89
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Fix unittest for CoalShiftQueue deq.valid change
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2023-04-28 00:50:34 -07:00 |
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Hansung Kim
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ec5c6ce08b
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Properly copy over queue data to inflight entry
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2023-04-28 00:50:19 -07:00 |
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Hansung Kim
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16c8eb2ada
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Fix old request not being invalidated; end-to-end flow working
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2023-04-27 21:54:02 -07:00 |
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Hansung Kim
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b5b1a7da66
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Add uncoalescer test case for all-lane-same-offset case
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2023-04-27 21:53:36 -07:00 |
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Hansung Kim
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edc05d51e6
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Fix not respecting invalidate.valid from coalescer
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2023-04-27 21:35:26 -07:00 |
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Hansung Kim
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7f821a66f5
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First attempt at hooking up coalescer to uncoalescer
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2023-04-27 21:19:56 -07:00 |
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Hansung Kim
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dfdd4f8342
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Redundant call syntax
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2023-04-27 20:36:04 -07:00 |
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Hansung Kim
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699520073e
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Make maxSize accessor function
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2023-04-27 20:34:20 -07:00 |
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Hansung Kim
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ba2bc3020b
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Fix truncation bug in matchCount
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2023-04-27 20:24:15 -07:00 |
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Hansung Kim
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84ac332637
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Add chiseltest for stride = 0
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2023-04-27 19:51:17 -07:00 |
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Hansung Kim
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7780250c7a
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More comments & renames
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2023-04-27 19:17:07 -07:00 |
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Richard Yan
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900f5adb20
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running coalescing flow
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2023-04-26 01:23:21 -07:00 |
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Hansung Kim
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4c1ae1cb3d
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More debug prints
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2023-04-25 19:15:28 -07:00 |
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Hansung Kim
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ef25c8a3f0
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Fix matchCount having bit width of 1 for spatial-only
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2023-04-25 18:46:26 -07:00 |
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Hansung Kim
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2090b8703e
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Rename params
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2023-04-25 17:16:28 -07:00 |
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Hansung Kim
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33f7adb5eb
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Make separate param for response depth queue
This is not necessarily the same as NUM_NEW_IDS, the latter determines
the inflight coalescing table size but not the response queues.
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2023-04-25 17:09:46 -07:00 |
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Hansung Kim
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980c77a8fa
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Renames
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2023-04-25 16:55:59 -07:00 |
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Hansung Kim
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9000577f45
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Add assertions for queue drift
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2023-04-25 14:36:52 -07:00 |
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Richard Yan
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99348e1e40
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mostly running coalescing test
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2023-04-25 02:50:14 -07:00 |
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Richard Yan
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3a0fdb2c67
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WIP diplomacy set up for coal unit test
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2023-04-25 02:26:13 -07:00 |
|
Richard Yan
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be40c77d06
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merge graphics
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2023-04-25 00:10:51 -07:00 |
|
Richard Yan
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37620400db
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WIP coalescing flow test
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2023-04-25 00:09:23 -07:00 |
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Hansung Kim
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31e04e9402
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Fix CoalShiftQueue invalidate logic
IO type change to Valid[UInt] was not reflected in the valid bit logic.
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2023-04-24 14:01:39 -07:00 |
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Hansung Kim
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7539c39c45
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Store SizeEnum in entry instead of UInt
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2023-04-23 22:34:19 -07:00 |
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Richard Yan
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5d105b36c5
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Merge branch 'richard-dev' into graphics
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2023-04-23 21:34:52 -07:00 |
|
Richard Yan
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a872856263
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quick coalescer connection fix
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2023-04-23 21:31:25 -07:00 |
|
Richard Yan
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7663a03a8c
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coalescer implementation passing compilation
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2023-04-23 21:29:07 -07:00 |
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Hansung Kim
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c21a196907
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scalafmt
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2023-04-23 20:56:55 -07:00 |
|
Richard Yan
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647d7b8628
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WIP multi-coalescer
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2023-04-23 20:31:54 -07:00 |
|
Richard Yan
|
bac8916ba1
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mono coalescer implementation
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2023-04-23 15:55:46 -07:00 |
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Hansung Kim
|
0f2e4ee8aa
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Store UInt instead of ChiselEnum in entry; pass tests
Scala isn't happy with storing ChiselEnum type for some reason
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2023-04-23 15:28:12 -07:00 |
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Hansung Kim
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8cee61a591
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Uncoalesce using table size enum
|
2023-04-23 14:42:10 -07:00 |
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