Hansung Kim
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773cfcbd6e
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Bump vortex for external smem
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2024-01-01 14:27:49 -08:00 |
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Hansung Kim
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8c12c7af16
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Instantiate multiple TLRAMs as sharedmem banks
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2024-01-01 12:49:23 -08:00 |
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Hansung Kim
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95e05f5457
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Connect smem core IO to TL with translation
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2024-01-01 02:24:57 -08:00 |
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Hansung Kim
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15c3c55cb6
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Make empty sharedmem diplomacy nodes
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2024-01-01 00:46:01 -08:00 |
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Hansung Kim
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cb2bc8cc0a
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Rename VortexBank -> VortexCache
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2024-01-01 00:08:25 -08:00 |
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Hansung Kim
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65446946be
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Bump vortex
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2023-12-10 05:58:21 -08:00 |
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Hansung Kim
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efac9b7d0b
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Better logic for {imem,dmem}TagWidth
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2023-12-10 05:58:00 -08:00 |
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Hansung Kim
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2879108804
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Accept coalescer enable at WithCoalescer config
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2023-12-01 19:01:06 -08:00 |
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Hansung Kim
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4eb9973b2c
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Attempt to replicate bitwidth logic for dmem/imem tag
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2023-11-29 15:13:17 -08:00 |
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Hansung Kim
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2bdaf3a0a8
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Fix undefined {MEM,WORD}_ADDR_SIZE
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2023-11-28 22:49:48 -08:00 |
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Hansung Kim
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0589b310f1
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Add missing parameters for VX_cache_top
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2023-11-28 20:32:49 -08:00 |
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Hansung Kim
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6248926b47
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Remove icache-specific address set and naming
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2023-11-28 20:08:46 -08:00 |
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Hansung Kim
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74fe530105
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Enable configuring MSHR size from Chisel
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2023-11-28 19:55:23 -08:00 |
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Hansung Kim
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f8d7169d19
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Delete old addResource for vortex v1
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2023-11-28 19:44:02 -08:00 |
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Hansung Kim
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4f274af363
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Bump vortex with way_idx revert
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2023-11-28 19:34:32 -08:00 |
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Hansung Kim
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4efe9cb93f
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Instantiate separate VortexL1Cache for imem and dmem
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2023-11-28 19:22:11 -08:00 |
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Hansung Kim
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0d60180d0d
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Change NUM_WAYS from 1 to 4
NUM_WAYS = 1 seem to be broken in Vortex. This makes sgemm test pass
|
2023-11-28 18:43:25 -08:00 |
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Hansung Kim
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d45cf835cf
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Remove dedicated icache bank from VortexBank
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2023-11-28 18:42:58 -08:00 |
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Hansung Kim
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b66be6c3ae
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Respect VX_cache's MEM_TAG_WIDTH; rename coalToVxCacheNode
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2023-11-28 16:54:50 -08:00 |
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Hansung Kim
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c5e37dd3b8
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Rename l2ReqSourceGenSize -> memSideSourceIds
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2023-11-28 14:55:52 -08:00 |
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Hansung Kim
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bd1aaaccfe
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Bump vortex with trace and CSR fix
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2023-11-28 12:52:23 -08:00 |
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Hansung Kim
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f187291a9c
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VortexBank: Update addResource for vortex2; WIP fix params
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2023-11-28 12:51:34 -08:00 |
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Hansung Kim
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8ed82e8261
|
Remove unclear size width requirement in tl adapter
|
2023-11-27 16:42:07 -08:00 |
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Hansung Kim
|
dafacf9873
|
Bump vortex
|
2023-11-19 17:55:23 -08:00 |
|
Hansung Kim
|
ccd6582991
|
Set correct mask for PutPartial for core writes
Previously byte-partial writes such as `sh` would not work correctly.
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2023-11-19 17:54:08 -08:00 |
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Hansung Kim
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d7cbf4916a
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Rename sourceWidth -> tagWidth
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2023-11-19 17:49:47 -08:00 |
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Hansung Kim
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1346f74210
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Bump vortex with tag width fix
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2023-11-17 19:13:48 -08:00 |
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Hansung Kim
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765c8ef1b0
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Remove unnecessary write ack filtering logic in VortexTLAdapter
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2023-11-17 19:12:35 -08:00 |
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Hansung Kim
|
6802d23598
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Change dcache sourceWidth constant to match DCACHE_NOSM_TAG_WIDTH
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2023-11-17 19:12:03 -08:00 |
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Hansung Kim
|
05ffa884a6
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Bump vortex with DCR fix
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2023-11-16 18:00:56 -08:00 |
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Hansung Kim
|
65f4264d57
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Pass hang100 address to wrapper verilog
|
2023-11-16 18:00:40 -08:00 |
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Hansung Kim
|
dca74eface
|
Bump vortex to 2.0
|
2023-11-15 22:06:17 -08:00 |
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Hansung Kim
|
134dd4eb59
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Update BlackBox to include Vortex 2.0
|
2023-11-15 21:58:40 -08:00 |
|
Hansung Kim
|
0768a7abc9
|
More cleanup and doc
|
2023-11-10 18:49:11 -08:00 |
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Hansung Kim
|
0bb8e6d705
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Bump vortex with ibuffer size fix
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2023-11-10 18:38:59 -08:00 |
|
Hansung Kim
|
ecfa18ce69
|
Rename to VortexBank
|
2023-11-10 17:46:04 -08:00 |
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Hansung Kim
|
78e09160a2
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Rename L1System -> VortexL1; do not expose bank Xbar from L1
|
2023-11-10 16:11:43 -08:00 |
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Hansung Kim
|
257232dec8
|
Require MSHR size matches nSrcId to L2
|
2023-11-10 15:04:32 -08:00 |
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Hansung Kim
|
5adf334af4
|
Scalafmt & rename & update doc
|
2023-11-10 14:58:16 -08:00 |
|
Hansung Kim
|
d51ce4cfa8
|
Reformat
|
2023-11-10 14:46:33 -08:00 |
|
Hansung Kim
|
17a39a369f
|
Cleanup conditional L1 instantiation
|
2023-11-10 14:42:33 -08:00 |
|
Hansung Kim
|
a0c15b2cc3
|
Use separate {imem,dmem}SourceWidth to fix deadlock
imemSourceWidth cannot be larger than the ibuffer size.
|
2023-11-08 20:20:17 -08:00 |
|
Hansung Kim
|
2f205be702
|
Update docs
|
2023-11-08 14:03:14 -08:00 |
|
Hansung Kim
|
571d33a5de
|
Remove unused MSB offset code from get getCoalescedDataChunk
|
2023-11-08 14:03:14 -08:00 |
|
Vamber Yang
|
61aad0315c
|
L1 FatBank Integration, multi-bank working with 4 dcache banks, 1 icache bank
Merge remote-tracking branch 'remotes/origin/graphics' into local-graphics-dev
|
2023-11-06 21:56:11 -08:00 |
|
Vamber Yang
|
e958ede277
|
multi-bank working when nBanks=2, encountered a putPartial error, need to pull latest change
|
2023-11-06 20:51:23 -08:00 |
|
Vamber Yang
|
be5134cd8a
|
L1 fatbank works with 2^5 source bits in SourceGen, failed with < 2^4 source bits in SourceGen
|
2023-11-01 23:48:24 -07:00 |
|
Hansung Kim
|
d2bfc31592
|
Fix store opcode assertion in AOpcodeIsStore
Now we support PutPartialData for narrow write requests that doesn't have all-1
mask.
|
2023-10-31 23:06:35 -07:00 |
|
Vamber Yang
|
75adb1dc66
|
Intergation of L1 Fatbank
|
2023-10-31 16:14:34 -07:00 |
|
Hansung Kim
|
635f4e42ff
|
Add detailed doc on source allocation/filtering
|
2023-10-25 20:55:01 -07:00 |
|