Hansung Kim
0c0a8ec553
SimMemTraceLogger: store handle in class
2023-04-23 11:27:06 -07:00
Hansung Kim
8a7e6f1391
Replace hardcoded trace widths with proper params
2023-04-21 18:20:16 -07:00
Hansung Kim
3f9f7a1d67
Generate proper AccessAck/AccessAckData from response queue
2023-04-21 16:14:52 -07:00
Hansung Kim
02ce969c67
Fix width mismatch for source logger
2023-04-17 18:52:38 -07:00
Hansung Kim
d4a51cfee5
Log source ID in the trace
2023-04-17 18:43:17 -07:00
Hansung Kim
41d520a991
Log both request and response in trace logger
...
Inside DPI code, have a vector of unique_ptrs that act as handles to multiple
different trace logger instances. Each logger instance is instantiated in a
single instance of the Verilog module, and multiple of these Verilog modules may
be instantiated in the Chisel module (see simReq and simResp in MemTraceLogger).
2023-04-17 18:10:13 -07:00
Hansung Kim
8978c2a812
trait HasTraceReq
2023-04-17 16:51:37 -07:00
Hansung Kim
f60602fc34
Write trace from logger in the same format as driver
2023-04-17 16:26:25 -07:00
Hansung Kim
282434eb7d
Basic C++ file IO for trace logger
2023-04-17 16:20:27 -07:00
Hansung Kim
8e763b512a
Relay full trace line info to DPI
2023-04-12 13:54:59 -07:00
Hansung Kim
1057ed59d3
Parse log2(size) from trace; set is_store from TL opcode
2023-04-11 18:23:50 -07:00
Hansung Kim
71f334bb22
Fix size parsing from memtrace
2023-04-11 17:36:45 -07:00
Hansung Kim
dca52ace0b
Fix verilog lint error
2023-04-10 20:37:26 -07:00
Hansung Kim
b53711965e
Connect TL edge data to SimMemTraceLogger
...
TODO: since TileLink rounds all address down to a multiple of its beat
size (8 in the current code), we can't directly compare the memory trace
input to its output. Need to take masks into account.
2023-04-10 20:24:27 -07:00
Hansung Kim
af29acdcda
Placeholder for MemTraceLogger C++ code
2023-04-09 14:53:02 -07:00
Vamber Yang
8e5254292b
Attach MemTracer to SBus , all physical addr hashed between 0X80000000->0X90000000
2023-04-05 23:43:22 -07:00
Hansung Kim
bdc32b765f
Accept memory trace filename from VCS plusargs
...
Now can use `EXTRA_SIM_FLAGS="+memtracefile=<tracefile>"` to simulate
with different trace files without recompiling.
2023-04-03 17:41:47 -07:00
Hansung Kim
9bfb813e1b
Thread -> Lane
...
"thread" is confusing, unify to lane when denoting a hardware SIMD lane
inside a single warp.
2023-03-09 22:09:21 -08:00
Vamber Yang
0de09daa05
MemTracer able to read and write according to trace file, also support thread_id skipping in trace file
2023-03-08 17:34:10 -08:00
Hansung Kim
41ecf6bc20
Squelch debug prints in SimMemTrace
2023-03-07 17:53:09 -08:00
Hansung Kim
db9be56191
Properly connect each lane to TL node
2023-03-05 00:18:29 -08:00
Hansung Kim
172ab51355
Fix formatting and unused warnings
2023-03-03 23:44:50 -08:00
Hansung Kim
5f55a7578f
Recover lost changes
2023-03-03 22:36:54 -08:00
Hansung Kim
dcb49f7683
Doc update
2023-03-03 21:22:56 -08:00
Hansung Kim
9025729c0e
Emit address in addition to cycle
2023-02-27 17:36:54 -08:00
Hansung Kim
0ebaed5f1b
Communicate trace cycle data from C++ to Chisel
2023-02-27 14:40:49 -08:00
Hansung Kim
72de4bca66
Initial parsing of memory trace file in C++
2023-02-27 13:47:30 -08:00
Hansung Kim
80e4b5c734
Set up simple DPI for trace-driven testing
2023-02-26 20:39:19 -08:00
