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  • 01ae6ffafe Added Core Interface felsabbagh3 2020-03-03 22:14:56 -08:00
  • 57a96e02b1 Fixed some other timing issues felsabbagh3 2020-03-03 21:15:44 -08:00
  • 58db00f555 Fixed some other timing issues felsabbagh3 2020-03-03 21:15:44 -08:00
  • 08986bf1dc Fixed incorrect valid and'ing in execute felsabbagh3 2020-03-03 20:57:20 -08:00
  • 25b6dbdfa8 Fixed incorrect valid and'ing in execute felsabbagh3 2020-03-03 20:57:20 -08:00
  • a47f7c11ec Finished cache, dram imp + interfaces left felsabbagh3 2020-03-03 19:42:33 -08:00
  • 733d00aba9 Finished cache, dram imp + interfaces left felsabbagh3 2020-03-03 19:42:33 -08:00
  • 8ece8d8893 Fixed miss reserv to support ST->LD sequences felsabbagh3 2020-03-03 17:04:39 -08:00
  • e2e053ff7b Fixed miss reserv to support ST->LD sequences felsabbagh3 2020-03-03 17:04:39 -08:00
  • 80af320fdb Before fixing miss rsrv for ST->LD sequences felsabbagh3 2020-03-03 16:57:05 -08:00
  • b150327ca9 Before fixing miss rsrv for ST->LD sequences felsabbagh3 2020-03-03 16:57:05 -08:00
  • 361fc2c3fe Finished st0 felsabbagh3 2020-03-03 02:49:30 -08:00
  • 8784b09b18 Finished st0 felsabbagh3 2020-03-03 02:49:30 -08:00
  • 3a970bbe7b Connected cache to bank felsabbagh3 2020-03-02 23:24:17 -08:00
  • 8c6284f627 Connected cache to bank felsabbagh3 2020-03-02 23:24:17 -08:00
  • fc5621cd1d Everything except bank internals felsabbagh3 2020-03-02 23:08:54 -08:00
  • f6cc05eaa2 Everything except bank internals felsabbagh3 2020-03-02 23:08:54 -08:00
  • abca2f7abb Modified Scheduler to be mask based (allows thread granuility writebacks) + Fixed all LW and SW unit test errors errors felsabbagh3 2020-03-01 22:27:18 -08:00
  • d78338c7d4 Modified Scheduler to be mask based (allows thread granuility writebacks) + Fixed all LW and SW unit test errors errors felsabbagh3 2020-03-01 22:27:18 -08:00
  • 6bf25b5b78 +Added icache stage -- 3rd case of AUIPC os broken? felsabbagh3 2020-03-01 18:01:02 -08:00
  • f98f5c414d +Added icache stage -- 3rd case of AUIPC os broken? felsabbagh3 2020-03-01 18:01:02 -08:00
  • 857bb54f3f remove temp files Blaise Tine 2020-03-01 00:30:36 -05:00
  • ef2c8f3cb9 Update rv32ui test files Merge branch 'master' of https://github.gatech.edu/casl/Vortex Ruei-Ting Chien 2020-02-23 02:23:27 -05:00
  • acb39ae6d9 Add up-to-date rv32ui unit test and dump files Ruei-Ting Chien 2020-02-23 02:22:43 -05:00
  • 23aabbf01d Make ALU div/mul pipelines longer and support logic element multiplication mode for better long pipeline performance wgulian3 2020-02-22 20:16:13 -05:00
  • ca61801199 Make ALU div/mul pipelines longer and support logic element multiplication mode for better long pipeline performance wgulian3 2020-02-22 20:16:13 -05:00
  • b2afe526fe Update multiply for not SYN_FUNC wgulian3 2020-02-21 23:20:04 -05:00
  • a099cb25cf Update multiply for not SYN_FUNC wgulian3 2020-02-21 23:20:04 -05:00
  • f2c0453702 Add multi-cycle compat module and use it in ALU wgulian3 2020-02-21 20:50:14 -05:00
  • 2c40874cc5 Add multi-cycle compat module and use it in ALU wgulian3 2020-02-21 20:50:14 -05:00
  • 83d1f54fcf fix shared mem ram inference wgulian3 2020-02-20 15:59:23 -05:00
  • e145b8078c fix shared mem ram inference wgulian3 2020-02-20 15:59:23 -05:00
  • 55d722364d Merge branch 'fpga_synthesis' into fix_cache_m10k wgulian3 2020-02-20 02:36:39 -05:00
  • 2d3b790324 Merge branch 'fpga_synthesis' into fix_cache_m10k wgulian3 2020-02-20 02:36:39 -05:00
  • e82e29c855 remove async reset for FPGA synthesis codetector 2020-02-19 23:19:05 -05:00
  • e901fb6a3a remove async reset for FPGA synthesis codetector 2020-02-19 23:19:05 -05:00
  • de85cfd296 fix clean build with makefile wgulian3 2020-02-19 17:33:51 -05:00
  • 072c89c433 Merge branch 'fpga_synthesis' into fix_cache_m10k Codetector 2020-02-19 16:03:23 -05:00
  • 1a29007bc7 Merge branch 'fpga_synthesis' into fix_cache_m10k Codetector 2020-02-19 16:03:23 -05:00
  • 5dadeffac8 fix project.tcl wgulian3 2020-02-19 14:20:58 -05:00
  • 3b60c10460 Merge branch 'fpga_synthesis' of github.gatech.edu:casl/Vortex into fpga_synthesis wgulian3 2020-02-19 01:04:55 -05:00
  • 3423e3189f Fix e2e building issues and increase division pipeline length wgulian3 2020-02-19 01:04:48 -05:00
  • e997494d41 Update needed trmontgomery 2020-02-18 19:42:10 -05:00
  • 3e68c8bcf5 verilator does not support delayed assignment in a loop wgulian3 2020-02-18 13:38:17 -05:00
  • e76d05f7ce Fix issues quartus synthesis issues wgulian3 2020-02-18 13:24:18 -05:00
  • d71f8fcc73 Fix divide edge case in verilator and move divide modules out of SYN_FUNC block within alu. wgulian3 2020-02-18 13:02:46 -05:00
  • a32d654263 Merge branch 'master' into fpga_synthesis wgulian3 2020-02-18 03:35:12 -05:00
  • 61803741f8 Merge branch 'master' into fpga_synthesis wgulian3 2020-02-18 03:34:38 -05:00
  • 28ce40eebf fixed make w + vx_gpr_stage csr schedule felsabbagh3 2020-02-18 00:26:44 -08:00
  • be66e51613 Added CSRs, some Load unit tests are failing felsabbagh3 2020-02-17 22:22:27 -08:00
  • a0f3f67426 Fixed double printing in ::io_handler felsabbagh3 2020-02-17 19:47:55 -08:00
  • 551c4aa2e9 Merge branch 'master' of https://github.gatech.edu/casl/Vortex felsabbagh3 2020-02-17 19:36:17 -08:00
  • 3a45375596 Fixed Verilator felsabbagh3 2020-02-17 19:36:00 -08:00
  • 3aa4c26eb9 minor fix Blaise Tine 2020-02-17 20:36:16 -05:00
  • 90c3813340 fixed all C++ extra + pedantic errors Blaise Tine 2020-02-17 15:02:06 -05:00
  • 4184980188 verilator: run all riscv tests wgulian3 2020-02-13 13:50:57 -05:00
  • e662ef4134 Fix verilator wgulian3 2020-02-13 13:18:06 -05:00
  • 86bfa4d1e4 Fix verilator wgulian3 2020-02-13 13:18:06 -05:00
  • 8318aff69f Support exec multi-cycle for div/mul wgulian3 2020-02-13 13:17:46 -05:00
  • ded06bcd12 ram m10k fix codetector 2020-02-11 09:57:32 -05:00
  • f1673726b2 ram m10k fix codetector 2020-02-11 09:57:32 -05:00
  • c1bd731d7f Add ram async clear port fix for fpga RAM inference wgulian3 2020-02-06 13:07:50 -05:00
  • 9c7a9d88cf Replace div/rem expressions with divider modules in preparation for pipelining wgulian3 2020-02-04 11:54:06 -05:00
  • 0211ca4add Add compat divide module and tb wgulian3 2020-02-04 10:59:05 -05:00
  • 8d20b52ea2 Cleanup imports of VX_define wgulian3 2020-02-04 10:54:25 -05:00
  • 0e0ea52568 Merge pull request #1 from casl/OPAE Elsabbagh, Fares Ehab Mohamed Abouelnasr 2020-01-30 13:45:05 -08:00
  • 2eed4e68be Create opae_setup.sh Apurve Chawda 2020-01-30 16:41:37 -05:00
  • cd07b508fa Update README.md Tine, Blaise 2020-01-29 15:39:33 -05:00
  • d727404f3b timing analysis tcl wgulian3 2020-01-28 04:09:00 -05:00
  • 4158b29f29 Fancier SDC file wgulian3 2020-01-28 02:20:13 -05:00
  • a6e74f589e Update files wgulian3 2020-01-27 20:35:45 -05:00
  • ca283f39eb Update README.md Tine, Blaise 2020-01-27 03:42:36 -05:00
  • 9b66bb4ed4 Update README.md Tine, Blaise 2020-01-27 01:46:31 -05:00
  • 7abd355b05 Updated MakeFile path trmontgomery 2020-01-26 11:27:40 -05:00
  • 12a4136464 quartus makefile: Support custom Quartus root location wgulian3 2020-01-24 18:38:39 -05:00
  • e9cdc6e5af SystemVerilog tweaks to appease Quartus and make Quartus synthesis work wgulian3 2020-01-24 06:08:00 -05:00
  • 229d76ff23 update Blaise Tine 2020-01-22 00:56:03 -05:00
  • 383bc15794 update Blaise Tine 2020-01-22 00:49:23 -05:00
  • df435ffa97 update README Blaise Tine 2020-01-22 00:47:57 -05:00
  • 43d5612a6b updated README Blaise Tine 2020-01-21 21:23:00 -05:00
  • 759349f2bf updated README and Makefile environment settings Blaise Tine 2020-01-21 21:21:56 -05:00
  • 60f0cfe215 Create LICENSE Tine, Blaise 2020-01-11 11:00:37 -05:00
  • db3a9e4f73 Update README.md Tine, Blaise 2020-01-11 10:59:46 -05:00
  • ad7f2518ed Delete .DS_Store Tine, Blaise 2020-01-11 10:47:22 -05:00
  • e38bdcdb33 Delete sftp-config.json Tine, Blaise 2020-01-11 10:46:57 -05:00
  • 0aa5f1fb40 Delete results.txt Tine, Blaise 2020-01-11 10:46:48 -05:00
  • 0c886a8989 Update README.md Tine, Blaise 2020-01-11 10:40:26 -05:00
  • 35088b6e1a update Blaise Tine 2020-01-11 10:06:14 -05:00
  • 33c882f9e8 Delete dummy.txt Tine, Blaise 2020-01-11 09:41:28 -05:00
  • 9ec835c8f7 Delete stylesheet.css Tine, Blaise 2020-01-11 09:41:12 -05:00
  • e1bd0e568f Delete normalize.css Tine, Blaise 2020-01-11 09:40:58 -05:00
  • 21cc548229 Delete github-light.css Tine, Blaise 2020-01-11 09:40:48 -05:00
  • 3246832347 Delete params.json Tine, Blaise 2020-01-11 09:40:14 -05:00
  • 0a1ae82363 Delete index.html Tine, Blaise 2020-01-11 09:39:57 -05:00
  • bd9200236d Create dummy.txt Tine, Blaise 2020-01-11 08:18:06 -05:00
  • a8627a6230 Create master branch via GitHub Tine, Blaise 2020-01-11 08:09:19 -05:00
  • 374d991a20 Vector evaluations proshan3 2019-11-25 22:18:12 -05:00
  • 72361b3afe merging error fixed Euna Kim 2019-11-25 20:53:41 -05:00
  • a9970ae62f Merge branch 'master' of https://github.gatech.edu/casl/Vortex Blaise Tine 2019-11-25 18:49:15 -05:00
  • e3b8b375ef lbm Blaise Tine 2019-11-25 18:48:48 -05:00