wu-arch/kernels
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge branch 'master' of https://github.gatech.edu/casl/Vortex

Browse Source
This commit is contained in:
felsabbagh3
2020-02-17 19:36:17 -08:00
parent 3a45375596 3aa4c26eb9
commit 551c4aa2e9
25 changed files with 141 additions and 98 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
emulator/enc.cpp
View File

@@ -24,7 +24,7 @@ ByteDecoder::ByteDecoder(const ArchDef &ad) {
static void decodeError(string msg) {
cout << "Instruction decoder error: " << msg << '\n';
exit(1);
std::abort();
}
void Encoder::encodeChunk(DataChunk &dest, const TextChunk &src) {
@@ -386,7 +386,7 @@ Instruction *WordDecoder::decode(const std::vector<Byte> &v, Size &idx) {
break;
defualt:
cout << "Unrecognized argument class in word decoder.\n";
exit(1);
std::abort();
}
if (haveRefs && usedImm && refMap.find(idx-n/8) != refMap.end()) {

2
emulator/include/mem.h
View File

@@ -359,7 +359,7 @@ namespace Harp {
char* content = new char[size];
int x = fread(content, 1, size, fp);
if (!x) { std::cout << "COULD NOT READ FILE\n"; exit(1);}
if (!x) { std::cout << "COULD NOT READ FILE\n"; std::abort();}
int offset = 0;
char* line = content;

4
emulator/include/obj.h
View File

@@ -40,7 +40,7 @@ namespace Harp {
Ref(name, rel), addr(addr) { }
virtual void bind(Addr addr, Addr base = 0) {
std::cout << "Attempted to bind a SimpleRef.\n";
exit(1);
std::abort();
}
virtual Addr getAddr() const { return this->addr; }
Byte *getAddrPtr() { return (Byte*)&addr; }
@@ -86,7 +86,7 @@ namespace Harp {
// std::cout << "Attempt to bind a " << bits << "-bit "
// << (relative?"":"non-") << "relative symbol to an address"
// " it cannot reach.\n";
// exit(1);
// std::abort();
// }
// virtual Addr getAddr() const {

12
emulator/instruction.cpp
View File

@@ -284,7 +284,7 @@ void Instruction::executeOn(Warp &c) {
break;
default:
cout << "unsupported MUL/DIV instr\n";
exit(1);
std::abort();
}
}
else
@@ -351,7 +351,7 @@ void Instruction::executeOn(Warp &c) {
break;
default:
cout << "ERROR: UNSUPPORTED R INST\n";
exit(1);
std::abort();
}
}
break;
@@ -388,7 +388,7 @@ void Instruction::executeOn(Warp &c) {
break;
default:
cout << "ERROR: UNSUPPORTED L INST\n";
exit(1);
std::abort();
c.memAccesses.push_back(Warp::MemAccess(false, memAddr));
}
break;
@@ -475,7 +475,7 @@ void Instruction::executeOn(Warp &c) {
break;
default:
cout << "ERROR: UNSUPPORTED L INST\n";
exit(1);
std::abort();
}
break;
case S_INST:
@@ -507,7 +507,7 @@ void Instruction::executeOn(Warp &c) {
break;
default:
cout << "ERROR: UNSUPPORTED S INST\n";
exit(1);
std::abort();
}
c.memAccesses.push_back(Warp::MemAccess(true, memAddr));
#ifdef EMU_INSTRUMENTATION
@@ -855,7 +855,7 @@ void Instruction::executeOn(Warp &c) {
default:
cout << "pc: " << hex << (c.pc) << "\n";
cout << "aERROR: Unsupported instruction: " << *this << "\n" << flush;
exit(1);
std::abort();
}
}

6
emulator/mem.cpp
View File

@@ -25,7 +25,7 @@ RamMemDevice::RamMemDevice(const char *filename, Size wordSize) :
if (!input) {
cout << "Error reading file \"" << filename << "\" into RamMemDevice.\n";
exit(1);
std::abort();
}
do { contents.push_back(input.get()); } while (input);
@@ -38,7 +38,7 @@ RamMemDevice::RamMemDevice(Size size, Size wordSize) :
void RomMemDevice::write(Addr, Word) {
cout << "Attempt to write to ROM.\n";
exit(1);
std::abort();
}
Word RamMemDevice::read(Addr addr) {
@@ -215,7 +215,7 @@ Word DiskControllerMemDevice::read(Addr a) {
case 5: return status;
default:
cout << "Attempt to read invalid disk controller register.\n";
exit(1);
std::abort();
}
}

2
emulator/qsim-harp.cpp
View File

@@ -20,7 +20,7 @@ Harp::OSDomain::OSDomain(ArchDef &archref, string imgFile) :
{
if (osDomain != NULL) {
cout << "Error: OSDomain is a singleton.";
exit(1);
std::abort();
}
osDomain = this;

8
simX/Makefile
View File

@@ -1,7 +1,9 @@
################################################################################
# HARPtools by Chad D. Kersey, Summer 2011 #
################################################################################
CXXFLAGS ?= -std=c++11 -fPIC -O3 -g # -g -DUSE_DEBUG=3 -DPRINT_ACTIVE_THREADS
CXXFLAGS ?= -std=c++11 -fPIC -O3 -Wall -Wextra -pedantic -g -DUSE_DEBUG=3 -DPRINT_ACTIVE_THREADS
# CXXFLAGS ?= -std=c++11 -fPIC -O0 -g -Wall -Wextra -pedantic # -g -DUSE_DEBUG=3 -DPRINT_ACTIVE_THREADS
LIB_OBJS=simX.cpp args.cpp mem.cpp core.cpp instruction.cpp enc.cpp util.cpp
@@ -10,7 +12,9 @@ INCLUDE=-I. -I../rtl/shared_memory -I../rtl/cache -I../rtl/interfaces -Isimulate
FILE=cache_simX.v
COMP=--compiler gcc
LIB=
CF=-CFLAGS '-std=c++11 -fPIC -O3'
CF=-CFLAGS '-std=c++11 -fPIC -O3 -Wall -Wextra -pedantic'
#CF=-CFLAGS '-std=c++11 -fPIC -O0 -g -Wall -Wextra -pedantic'
LIGHTW=-Wno-UNOPTFLAT -Wno-WIDTH
DEB=--trace -DVL_DEBUG=1

37
simX/core.cpp
View File

@@ -111,6 +111,14 @@ Core::Core(const ArchDef &a, Decoder &d, MemoryUnit &mem, Word id):
release_warp = false;
foundSchedule = true;
schedule_w = 0;
memset(&inst_in_fetch, 0, sizeof(inst_in_fetch));
memset(&inst_in_decode, 0, sizeof(inst_in_decode));
memset(&inst_in_scheduler, 0, sizeof(inst_in_scheduler));
memset(&inst_in_exe, 0, sizeof(inst_in_exe));
memset(&inst_in_lsu, 0, sizeof(inst_in_lsu));
memset(&inst_in_wb, 0, sizeof(inst_in_wb));
INIT_TRACE(inst_in_fetch);
INIT_TRACE(inst_in_decode);
INIT_TRACE(inst_in_scheduler);
@@ -158,6 +166,7 @@ Core::Core(const ArchDef &a, Decoder &d, MemoryUnit &mem, Word id):
bool Core::interrupt(Word r0) {
w[0].interrupt(r0);
return false;
}
void Core::step()
@@ -214,8 +223,8 @@ void Core::getCacheDelays(trace_inst_t * trace_inst)
if (trace_inst->valid_inst)
{
bool in_dcache_in_valid[a.getNThds()];
unsigned in_dcache_in_address[a.getNThds()];
std::vector<bool> in_dcache_in_valid(a.getNThds());
std::vector<unsigned> in_dcache_in_address(a.getNThds());
unsigned in_dcache_mem_read;
unsigned in_dcache_mem_write;
@@ -709,10 +718,26 @@ void Core::printStats() const {
}
Warp::Warp(Core *c, Word id) :
core(c), pc(0x80000000), interruptEnable(true),
supervisorMode(true), activeThreads(0), reg(0), pred(0),
shadowReg(core->a.getNRegs()), shadowPReg(core->a.getNPRegs()), id(id),
spawned(false), steps(0), insts(0), loads(0), stores(0), VLEN(1024)
core(c),
pc(0x80000000),
shadowPc(0),
id(id),
activeThreads(0),
shadowActiveThreads(0),
reg(0),
pred(0),
shadowReg(core->a.getNRegs()),
shadowPReg(core->a.getNPRegs()),
VLEN(1024),
interruptEnable(true),
shadowInterruptEnable(false),
supervisorMode(true),
shadowSupervisorMode(false),
spawned(false),
steps(0),
insts(0),
loads(0),
stores(0)
{
D(3, "Creating a new thread with PC: " << hex << this->pc << '\n');
/* Build the register file. */

22
simX/enc.cpp
View File

@@ -22,14 +22,12 @@ using namespace Harp;
// wordSize = ad.getWordSize();
// }
static void decodeError(string msg) {
/*static void decodeError(string msg) {
cout << "Instruction decoder error: " << msg << '\n';
exit(1);
}
std::abort();
}*/
static unsigned ceilLog2(RegNum x) {
/*static unsigned ceilLog2(RegNum x) {
unsigned z = 0;
bool nonZeroInnerValues(false);
@@ -44,8 +42,7 @@ static unsigned ceilLog2(RegNum x) {
if (nonZeroInnerValues) z++;
return z;
}
}*/
WordDecoder::WordDecoder(const ArchDef &arch) {
@@ -236,7 +233,7 @@ Instruction *WordDecoder::decode(const std::vector<Byte> &v, Size &idx, trace_in
case InstType::V_TYPE:
D(3, "Entered here: instr type = vector" << op);
switch(op) {
switch (op) {
case Opcode::VSET_ARITH: //TODO: arithmetic ops
inst.setDestReg((code>>shift_rd) & reg_mask);
inst.setSrcReg((code>>shift_rs1) & reg_mask);
@@ -308,11 +305,14 @@ Instruction *WordDecoder::decode(const std::vector<Byte> &v, Size &idx, trace_in
//trace_inst->vd = ((code>>shift_rd) & reg_mask);
trace_inst->vs1 = ((code>>shift_rd) & reg_mask); //vs3
break;
default:
cout << "Inavlid opcode.\n";
std::abort();
}
break;
default:
default:
cout << "Unrecognized argument class in word decoder.\n";
exit(1);
std::abort();
}
if (haveRefs && usedImm && refMap.find(idx-n/8) != refMap.end()) {

2
simX/include/archdef.h
View File

@@ -111,6 +111,6 @@ namespace Harp {
RegNum nRegs, nPRegs;
char encChar;
};
};
}
#endif

2
simX/include/args.h
View File

@@ -56,6 +56,6 @@ namespace HarpTools {
bool &x;
};
};
}
#endif

2
simX/include/asm-tokens.h
View File

@@ -11,6 +11,6 @@ namespace HarpTools {
ASM_T_PREG, ASM_T_REG, ASM_T_REG_RA, ASM_T_REG_SP,
ASM_T_REG_FP, ASM_T_LIT, ASM_T_SYM, ASM_T_PEXP
};
};
}
#endif

19
simX/include/core.h
View File

@@ -35,9 +35,9 @@ namespace Harp {
template <typename T> class Reg {
public:
Reg(): cpuId(0), regNum(0), val(0) {}
Reg(Word c, Word n): cpuId(c), regNum(n), val(0) {}
Reg(Word c, Word n, T v): cpuId(c), regNum(n), val(v) {}
Reg(): val(0), cpuId(0), regNum(0) {}
Reg(Word c, Word n): val(0), cpuId(c), regNum(n) {}
Reg(Word c, Word n, T v): val(v), cpuId(c), regNum(n) {}
Reg &operator=(T r) { if (regNum) {val = r; doWrite();} return *this; }
@@ -83,10 +83,10 @@ namespace Harp {
DomStackEntry(const std::vector<bool> &tmask):
tmask(tmask), fallThrough(true), uni(false) {}
bool fallThrough;
bool uni;
std::vector<bool> tmask;
std::vector<bool> tmask;
Word pc;
bool fallThrough;
bool uni;
};
struct vtype
@@ -193,13 +193,14 @@ namespace Harp {
std::vector<std::vector<Reg<char*>>> vreg; // 32 vector registers
bool interruptEnable, shadowInterruptEnable, supervisorMode,
shadowSupervisorMode, spawned;
bool interruptEnable, shadowInterruptEnable;
bool supervisorMode, shadowSupervisorMode;
bool spawned;
unsigned long steps, insts, loads, stores;
friend class Instruction;
};
};
}
#endif

7
simX/include/enc.h
View File

@@ -50,7 +50,10 @@ namespace Harp {
public:
WordDecoder(const ArchDef &);
virtual Instruction *decode(const std::vector<Byte> &v, Size &n, trace_inst_t * trace_inst);
virtual Instruction *decode(const std::vector<Byte> &v, Size &n) {printf("Not implemented\n");}
virtual Instruction *decode(const std::vector<Byte> &v, Size &n) {
printf("Not implemented\n");
return nullptr;
}
private:
Size n, o, r, p, i1, i2, i3;
@@ -72,6 +75,6 @@ namespace Harp {
};
};
}
#endif

4
simX/include/harpfloat.h
View File

@@ -64,7 +64,7 @@ namespace Harp {
DEBUGMSG("Set to " << d);
}
Float(double d, Size n): sz(n), d(d) { DEBUGMSG("Float(double, size)"); }
Float(double d, Size n): d(d), sz(n) { DEBUGMSG("Float(double, size)"); }
operator Word_u() {
DEBUGMSG("Float -> Word_u: " << d);
@@ -120,4 +120,4 @@ namespace Harp {
double d;
Size sz;
};
};
}

4
simX/include/help.h
View File

@@ -32,6 +32,6 @@ namespace HarpTools {
*disasmHelp = "HARP Disassembler command line arguments:\n"
" -a, --arch <arch string> Architecture string.\n"
" -o, --output <filename> Output filename.\n";
};
};
}
}
#endif

2
simX/include/instruction.h
View File

@@ -164,7 +164,7 @@ namespace Harp {
};
};
}
#endif

27
simX/include/mem.h
View File

@@ -99,9 +99,10 @@ namespace Harp {
Byte *file;
Size blocks;
};
std::vector <Disk> disks;
Size wordSize, blockSize;
Core &core;
Size wordSize, blockSize;;
std::vector <Disk> disks;
};
class MemoryUnit {
@@ -136,7 +137,7 @@ namespace Harp {
private:
class ADecoder {
public:
ADecoder() : zeroChild(NULL), oneChild(NULL), range(0) {}
ADecoder() : zeroChild(NULL), oneChild(NULL), range(0), md(nullptr) {}
ADecoder(MemDevice &md, Size range) :
zeroChild(NULL), oneChild(NULL), range(range), md(&md) {}
Byte *getPtr(Addr a, Size sz, Size wordSize);
@@ -145,24 +146,24 @@ namespace Harp {
void map(Addr a, MemDevice &md, Size range, Size bit);
private:
MemDevice &doLookup(Addr a, Size &bit);
ADecoder *zeroChild, *oneChild;
MemDevice *md;
ADecoder *zeroChild, *oneChild;
Size range;
MemDevice *md;
};
ADecoder ad;
struct TLBEntry {
TLBEntry() {}
TLBEntry(Word pfn, Word flags): pfn(pfn), flags(flags) {}
Word flags;
Word pfn;
Word flags;
};
std::map<Addr, TLBEntry> tlb;
TLBEntry tlbLookup(Addr vAddr, Word flagMask);
Size pageSize, addrBytes;
ADecoder ad;
std::map<Addr, TLBEntry> tlb;
TLBEntry tlbLookup(Addr vAddr, Word flagMask);
bool disableVm;
};
@@ -402,7 +403,7 @@ namespace Harp {
char* content = new char[size];
int x = fread(content, 1, size, fp);
if (!x) { std::cout << "COULD NOT READ FILE\n"; exit(1);}
if (!x) { std::cout << "COULD NOT READ FILE\n"; std::abort();}
int offset = 0;
char* line = content;
@@ -455,7 +456,7 @@ namespace Harp {
};
}
#endif

6
simX/include/obj.h
View File

@@ -40,7 +40,7 @@ namespace Harp {
Ref(name, rel), addr(addr) { }
virtual void bind(Addr addr, Addr base = 0) {
std::cout << "Attempted to bind a SimpleRef.\n";
exit(1);
std::abort();
}
virtual Addr getAddr() const { return this->addr; }
Byte *getAddrPtr() { return (Byte*)&addr; }
@@ -86,7 +86,7 @@ namespace Harp {
// std::cout << "Attempt to bind a " << bits << "-bit "
// << (relative?"":"non-") << "relative symbol to an address"
// " it cannot reach.\n";
// exit(1);
// std::abort();
// }
// virtual Addr getAddr() const {
@@ -205,6 +205,6 @@ namespace Harp {
// private:
// const ArchDef &arch;
// };
};
}
#endif

2
simX/include/types.h
View File

@@ -20,6 +20,6 @@ namespace Harp {
enum MemFlags {RD_USR = 1, WR_USR = 2, EX_USR = 4,
RD_SUP = 8, WR_SUP = 16, EX_SUP = 32};
};
}
#endif

2
simX/include/util.h
View File

@@ -19,6 +19,6 @@ namespace Harp {
Word_u readWord(const std::vector<Byte> &b, Size &n, Size wordSize);
void writeByte(std::vector<Byte> &p, Size &n, Byte b);
void writeWord(std::vector<Byte> &p, Size &n, Size wordSize, Word w);
};
}
#endif

28
simX/instruction.cpp
View File

@@ -264,16 +264,16 @@ void trap_to_simulator(Warp & c)
fstat(file, &st);
fprintf(stderr, "------------------------\n");
fprintf(stderr, "Size of struct: %x\n", sizeof(struct stat));
fprintf(stderr, "Size of struct: %ld\n", sizeof(struct stat));
fprintf(stderr, "st_mode: %x\n", st.st_mode);
fprintf(stderr, "st_dev: %x\n", st.st_dev);
fprintf(stderr, "st_ino: %x\n", st.st_ino);
fprintf(stderr, "st_dev: %ld\n", st.st_dev);
fprintf(stderr, "st_ino: %ld\n", st.st_ino);
fprintf(stderr, "st_uid: %x\n", st.st_uid);
fprintf(stderr, "st_gid: %x\n", st.st_gid);
fprintf(stderr, "st_rdev: %x\n", st.st_rdev);
fprintf(stderr, "st_size: %x\n", st.st_size);
fprintf(stderr, "st_blksize: %x\n", st.st_blksize);
fprintf(stderr, "st_blocks: %x\n", st.st_blocks);
fprintf(stderr, "st_rdev: %ld\n", st.st_rdev);
fprintf(stderr, "st_size: %ld\n", st.st_size);
fprintf(stderr, "st_blksize: %ld\n", st.st_blksize);
fprintf(stderr, "st_blocks: %ld\n", st.st_blocks);
fprintf(stderr, "^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n");
upload(&write_buffer, (char *) &st.st_mode , sizeof(st.st_mode), c);
@@ -517,7 +517,7 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) {
break;
default:
cout << "unsupported MUL/DIV instr\n";
exit(1);
std::abort();
}
}
else
@@ -584,7 +584,7 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) {
break;
default:
cout << "ERROR: UNSUPPORTED R INST\n";
exit(1);
std::abort();
}
}
break;
@@ -622,7 +622,7 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) {
break;
default:
cout << "ERROR: UNSUPPORTED L INST\n";
exit(1);
std::abort();
c.memAccesses.push_back(Warp::MemAccess(false, memAddr));
}
break;
@@ -709,7 +709,7 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) {
break;
default:
cout << "ERROR: UNSUPPORTED L INST\n";
exit(1);
std::abort();
}
break;
case S_INST:
@@ -743,7 +743,7 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) {
break;
default:
cout << "ERROR: UNSUPPORTED S INST\n";
exit(1);
std::abort();
}
c.memAccesses.push_back(Warp::MemAccess(true, memAddr));
#ifdef EMU_INSTRUMENTATION
@@ -2397,7 +2397,7 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) {
break;
default:
cout << "ERROR: UNSUPPORTED S INST\n" << flush;
exit(1);
std::abort();
}
// cout << "Loop finished" << endl;
// c.memAccesses.push_back(Warp::MemAccess(true, memAddr));
@@ -2408,7 +2408,7 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) {
default:
D(3, "pc: " << hex << (c.pc-4));
D(3, "aERROR: Unsupported instruction: " << *this);
exit(1);
std::abort();
}
// break;

9
simX/mem.cpp
View File

@@ -25,7 +25,7 @@ RamMemDevice::RamMemDevice(const char *filename, Size wordSize) :
if (!input) {
cout << "Error reading file \"" << filename << "\" into RamMemDevice.\n";
exit(1);
std::abort();
}
do { contents.push_back(input.get()); } while (input);
@@ -34,11 +34,11 @@ RamMemDevice::RamMemDevice(const char *filename, Size wordSize) :
}
RamMemDevice::RamMemDevice(Size size, Size wordSize) :
contents(size), wordSize(wordSize) {}
wordSize(wordSize), contents(size) {}
void RomMemDevice::write(Addr, Word) {
cout << "Attempt to write to ROM.\n";
exit(1);
std::abort();
}
Word RamMemDevice::read(Addr addr) {
@@ -216,6 +216,7 @@ void *Harp::consoleInputThread(void* arg_vp) {
// }
// cout << "Console input ended. Exiting.\n";
// exit(4);
return nullptr;
}
// ConsoleMemDevice::ConsoleMemDevice(Size wS, std::ostream &o, Core &core,
@@ -246,7 +247,7 @@ Word DiskControllerMemDevice::read(Addr a) {
case 5: return status;
default:
cout << "Attempt to read invalid disk controller register.\n";
exit(1);
std::abort();
}
}

24
simX/simX.cpp
View File

@@ -144,14 +144,22 @@ int main(int argc, char** argv) {
try {
switch (findMode(argc - 1, argv + 1)) {
case HARPTOOL_MODE_ASM: cout << "ASM not supported\n";
case HARPTOOL_MODE_DISASM: cout << "DISASM not supported\n";
case HARPTOOL_MODE_EMU: return emu_main (argc - 2, argv + 2);
case HARPTOOL_MODE_LD: cout << "LD not supported\n";
case HARPTOOL_MODE_HELP:
default:
cout << "Usage:\n" << Help::mainHelp;
return 0;
case HARPTOOL_MODE_ASM:
cout << "ASM not supported\n";
return -1;
case HARPTOOL_MODE_DISASM:
cout << "DISASM not supported\n";
return -1;
case HARPTOOL_MODE_EMU:
return emu_main(argc - 2, argv + 2);
case HARPTOOL_MODE_LD:
cout << "LD not supported\n";
return -1;
case HARPTOOL_MODE_HELP:
[[fallthrough]];
default:
cout << "Usage:\n" << Help::mainHelp;
return 0;
}
} catch (BadArg ba) {
cout << "Unrecognized argument \"" << ba.arg << "\".\n";

2
simX/util.cpp
View File

@@ -13,7 +13,7 @@ using namespace std;
// Make it easy for autotools-based build systems to detect this library.
extern "C" {
int harplib_present = 1;
};
}
void Harp::wordToBytes(Byte *b, Word_u w, Size wordSize) {
while (wordSize--) {