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SystemVerilog tweaks to appease Quartus and make Quartus synthesis work

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This commit is contained in:
wgulian3
2020-01-24 06:08:00 -05:00
parent 60f0cfe215
commit e9cdc6e5af
18 changed files with 1665 additions and 66 deletions
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9
rtl/VX_csr_wrapper.v
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@@ -11,15 +11,16 @@ module VX_csr_wrapper (
wire[`NT_M1:0][31:0] thread_ids;
wire[`NT_M1:0][31:0] warp_ids;
genvar cur_t;
for (cur_t = 0; cur_t < `NT; cur_t = cur_t + 1) begin
genvar cur_t, cur_tw;
generate
for (cur_t = 0; cur_t < `NT; cur_t = cur_t + 1) begin : thread_ids_init
assign thread_ids[cur_t] = cur_t;
end
genvar cur_tw;
for (cur_tw = 0; cur_tw < `NT; cur_tw = cur_tw + 1) begin
for (cur_tw = 0; cur_tw < `NT; cur_tw = cur_tw + 1) begin : warp_ids_init
assign warp_ids[cur_tw] = {{(31-`NW_M1){1'b0}}, VX_csr_req.warp_num};
end
endgenerate
assign VX_csr_wb.valid = VX_csr_req.valid;

30
rtl/VX_execute_unit.v
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@@ -43,20 +43,19 @@ module VX_execute_unit (
wire[`NT_M1:0][31:0] alu_result;
genvar index_out_reg;
generate
for (index_out_reg = 0; index_out_reg < `NT; index_out_reg = index_out_reg + 1)
begin
VX_alu vx_alu(
// .in_reg_data (in_reg_data[1:0]),
.in_1 (in_a_reg_data[index_out_reg]),
.in_2 (in_b_reg_data[index_out_reg]),
.in_rs2_src (in_rs2_src),
.in_itype_immed(in_itype_immed),
.in_upper_immed(in_upper_immed),
.in_alu_op (in_alu_op),
.in_curr_PC (in_curr_PC),
.out_alu_result(alu_result[index_out_reg])
);
end
for (index_out_reg = 0; index_out_reg < `NT; index_out_reg = index_out_reg + 1) begin : alu_defs
VX_alu vx_alu(
// .in_reg_data (in_reg_data[1:0]),
.in_1 (in_a_reg_data[index_out_reg]),
.in_2 (in_b_reg_data[index_out_reg]),
.in_rs2_src (in_rs2_src),
.in_itype_immed(in_itype_immed),
.in_upper_immed(in_upper_immed),
.in_alu_op (in_alu_op),
.in_curr_PC (in_curr_PC),
.out_alu_result(alu_result[index_out_reg])
);
end
endgenerate
@@ -89,8 +88,7 @@ module VX_execute_unit (
wire[`NT_M1:0][31:0] duplicate_PC_data;
genvar i;
generate
for (i = 0; i < `NT; i=i+1)
begin
for (i = 0; i < `NT; i=i+1) begin : pc_data_setup
assign duplicate_PC_data[i] = VX_exec_unit_req.PC_next;
end
endgenerate

14
rtl/VX_gpgpu_inst.v
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@@ -14,10 +14,11 @@ module VX_gpgpu_inst (
wire[`NT_M1:0] tmc_new_mask;
genvar curr_t;
for (curr_t = 0; curr_t < `NT; curr_t=curr_t+1)
begin
generate
for (curr_t = 0; curr_t < `NT; curr_t=curr_t+1) begin : tmc_new_mask_init
assign tmc_new_mask[curr_t] = curr_t < VX_gpu_inst_req.a_reg_data[0];
end
endgenerate
wire valid_inst = (|curr_valids);
@@ -33,10 +34,11 @@ module VX_gpgpu_inst (
wire[31:0] wspawn_pc = VX_gpu_inst_req.rd2;
wire[`NW-1:0] wspawn_new_active;
genvar curr_w;
for (curr_w = 0; curr_w < `NW; curr_w=curr_w+1)
begin
generate
for (curr_w = 0; curr_w < `NW; curr_w=curr_w+1) begin : wspawn_new_active_init
assign wspawn_new_active[curr_w] = curr_w < VX_gpu_inst_req.a_reg_data[0];
end
endgenerate
assign VX_warp_ctl.is_barrier = VX_gpu_inst_req.is_barrier && valid_inst;
@@ -54,12 +56,14 @@ module VX_gpgpu_inst (
// VX_gpu_inst_req.pc
genvar curr_s_t;
for (curr_s_t = 0; curr_s_t < `NT; curr_s_t=curr_s_t+1) begin
generate
for (curr_s_t = 0; curr_s_t < `NT; curr_s_t=curr_s_t+1) begin : masks_init
wire curr_bool = (VX_gpu_inst_req.a_reg_data[curr_s_t] == 32'b1);
assign split_new_use_mask[curr_s_t] = curr_valids[curr_s_t] & (curr_bool);
assign split_new_later_mask[curr_s_t] = curr_valids[curr_s_t] & (!curr_bool);
end
endgenerate
wire[$clog2(`NT):0] num_valids;

6
rtl/VX_gpr_wrapper.v
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@@ -17,9 +17,11 @@ module VX_gpr_wrapper (
wire[`NT_M1:0][31:0] jal_data;
genvar index;
for (index = 0; index <= `NT_M1; index = index + 1) begin
generate
for (index = 0; index <= `NT_M1; index = index + 1) begin : jal_data_assign
assign jal_data[index] = VX_gpr_jal.curr_PC;
end
endgenerate
`ifndef ASIC
@@ -47,7 +49,7 @@ module VX_gpr_wrapper (
genvar warp_index;
generate
for (warp_index = 0; warp_index < `NW; warp_index = warp_index + 1) begin
for (warp_index = 0; warp_index < `NW; warp_index = warp_index + 1) begin : warp_gprs
wire valid_write_request = warp_index == VX_writeback_inter.wb_warp_num;
VX_gpr vx_gpr(

4
rtl/VX_inst_multiplex.v
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@@ -22,11 +22,13 @@ module VX_inst_multiplex (
// wire is_gpu = 0;
genvar currT;
for (currT = 0; currT < `NT; currT = currT + 1) begin
generate
for (currT = 0; currT < `NT; currT = currT + 1) begin : mask_init
assign is_mem_mask[currT] = is_mem;
assign is_gpu_mask[currT] = is_gpu;
assign is_csr_mask[currT] = is_csr;
end
endgenerate
// LSU Unit
assign VX_lsu_req.valid = VX_bckE_req.valid & is_mem_mask;

4
rtl/VX_lsu.v
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@@ -56,13 +56,15 @@ module VX_lsu (
genvar index;
for (index = 0; index <= `NT_M1; index = index + 1) begin
generate
for (index = 0; index <= `NT_M1; index = index + 1) begin : dcache_reqs
assign VX_dcache_req.out_cache_driver_in_address[index] = use_address[index];
assign VX_dcache_req.out_cache_driver_in_data[index] = use_store_data[index];
assign VX_dcache_req.out_cache_driver_in_valid[index] = (use_valid[index]);
assign VX_mem_wb.loaded_data[index] = VX_dcache_rsp.in_cache_driver_out_data[index];
end
endgenerate
assign VX_dcache_req.out_cache_driver_in_mem_read = use_mem_read;
assign VX_dcache_req.out_cache_driver_in_mem_write = use_mem_write;

5
rtl/VX_lsu_addr_gen.v
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@@ -9,9 +9,10 @@ module VX_lsu_addr_gen (
genvar index;
for (index = 0; index < `NT; index = index + 1)
begin
generate
for (index = 0; index < `NT; index = index + 1) begin : addresses
assign address[index] = base_address[index] + offset;
end
endgenerate
endmodule

3
rtl/VX_warp.v
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@@ -49,8 +49,9 @@ module VX_warp (
genvar out_cur_th;
generate
for (out_cur_th = 0; out_cur_th < `NT; out_cur_th = out_cur_th+1)
for (out_cur_th = 0; out_cur_th < `NT; out_cur_th = out_cur_th+1) begin : out_valid_assign
assign out_valid[out_cur_th] = in_change_mask ? in_thread_mask[out_cur_th] : stall ? 1'b0 : valid[out_cur_th];
end
endgenerate

4
rtl/VX_warp_scheduler.v
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@@ -251,7 +251,8 @@ module VX_warp_scheduler (
genvar curr_warp;
for (curr_warp = 0; curr_warp < `NW; curr_warp = curr_warp + 1) begin
generate
for (curr_warp = 0; curr_warp < `NW; curr_warp = curr_warp + 1) begin : stacks
wire correct_warp_s = (curr_warp == split_warp_num);
wire correct_warp_j = (curr_warp == join_warp_num);
@@ -267,6 +268,7 @@ module VX_warp_scheduler (
.q2 (q2)
);
end
endgenerate
// wire should_stall = stall || (jal && (warp_to_schedule == jal_warp_num)) || (branch_dir && (warp_to_schedule == branch_warp_num));

10
rtl/Vortex.v
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@@ -123,8 +123,9 @@ VX_dram_req_rsp_inter #(
end
*/
for (curr_bank = 0; curr_bank < `DCACHE_BANKS; curr_bank = curr_bank + 1) begin
for (curr_word = 0; curr_word < `DCACHE_NUM_WORDS_PER_BLOCK; curr_word = curr_word + 1) begin
generate
for (curr_bank = 0; curr_bank < `DCACHE_BANKS; curr_bank = curr_bank + 1) begin : dcache_setup
for (curr_word = 0; curr_word < `DCACHE_NUM_WORDS_PER_BLOCK; curr_word = curr_word + 1) begin : dcache_banks_setup
assign o_m_writedata_d[curr_bank][curr_word] = VX_dram_req_rsp.o_m_writedata[curr_bank][curr_word];
assign VX_dram_req_rsp.i_m_readdata[curr_bank][curr_word] = i_m_readdata_d[curr_bank][curr_word]; // fixed
@@ -133,12 +134,13 @@ for (curr_bank = 0; curr_bank < `DCACHE_BANKS; curr_bank = curr_bank + 1) begin
end
for (curr_bank = 0; curr_bank < `ICACHE_BANKS; curr_bank = curr_bank + 1) begin
for (curr_word = 0; curr_word < `ICACHE_NUM_WORDS_PER_BLOCK; curr_word = curr_word + 1) begin
for (curr_bank = 0; curr_bank < `ICACHE_BANKS; curr_bank = curr_bank + 1) begin : icache_setup
for (curr_word = 0; curr_word < `ICACHE_NUM_WORDS_PER_BLOCK; curr_word = curr_word + 1) begin : icache_banks_setup
assign o_m_writedata_i[curr_bank][curr_word] = VX_dram_req_rsp_icache.o_m_writedata[curr_bank][curr_word];
assign VX_dram_req_rsp_icache.i_m_readdata[curr_bank][curr_word] = i_m_readdata_i[curr_bank][curr_word]; // fixed
end
end
endgenerate
/////////////////////////////////////////////////////////////////////////

4
rtl/cache/VX_Cache_Bank.v vendored
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@@ -201,7 +201,8 @@ module VX_Cache_Bank
wire[NUM_WORDS_PER_BLOCK-1:0][3:0] we;
wire[NUM_WORDS_PER_BLOCK-1:0][31:0] data_write;
genvar g;
for (g = 0; g < NUM_WORDS_PER_BLOCK; g = g + 1) begin
generate
for (g = 0; g < NUM_WORDS_PER_BLOCK; g = g + 1) begin : write_enables
wire normal_write = (read_or_write && ((access && (block_offset == g))) && !miss);
assign we[g] = (write_from_mem) ? 4'b1111 :
@@ -215,6 +216,7 @@ module VX_Cache_Bank
assign data_write[g] = write_from_mem ? fetched_writedata[g] : use_write_data;
assign way_to_update = evicted_way;
end
endgenerate
VX_cache_data_per_index #(

4
rtl/cache/VX_cache_data_per_index.v vendored
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@@ -59,6 +59,7 @@ module VX_cache_data_per_index
localparam SEND_MEM_REQ = 1; // Write back this block into memory
localparam RECIV_MEM_RSP = 2;
generate
if(CACHE_WAYS != 1) begin
VX_generic_priority_encoder #(.N(CACHE_WAYS)) valid_index
(
@@ -79,6 +80,7 @@ module VX_cache_data_per_index
assign invalid_found = (valid_use_per_way == 1'b0) ? 1 : 0;
assign invalid_index = 0;
end
endgenerate
@@ -105,6 +107,7 @@ module VX_cache_data_per_index
genvar ways;
generate
for(ways=0; ways < CACHE_WAYS; ways = ways + 1) begin : each_way
@@ -144,6 +147,7 @@ module VX_cache_data_per_index
.dirty_use (dirty_use_per_way[ways])
);
end
endgenerate
// always @(posedge clk or posedge rst) begin
// if (rst) begin

13
rtl/cache/VX_d_cache.v vendored
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@@ -161,8 +161,8 @@ module VX_d_cache
reg[NUM_REQ-1:0] debug_hit_per_bank_mask[CACHE_BANKS-1:0];
genvar bid;
for (bid = 0; bid < CACHE_BANKS; bid=bid+1)
begin
generate
for (bid = 0; bid < CACHE_BANKS; bid=bid+1) begin : chooose_threads
wire[NUM_REQ-1:0] use_threads_track_banks = thread_track_banks[bid];
wire[LOG_NUM_REQ-1:0] use_thread_index = index_per_bank[bid];
wire use_write_final_data = hit_per_bank[bid];
@@ -177,6 +177,7 @@ module VX_d_cache
assign debug_hit_per_bank_mask[bid] = {NUM_REQ{hit_per_bank[bid]}};
assign threads_serviced_per_bank[bid] = use_mask_per_bank[bid] & debug_hit_per_bank_mask[bid];
end
endgenerate
integer test_bid;
always @(*) begin
@@ -207,10 +208,11 @@ module VX_d_cache
genvar tid;
for (tid = 0; tid < NUM_REQ; tid =tid+1)
begin
generate
for (tid = 0; tid < NUM_REQ; tid =tid+1) begin : new_final_data_read_Qual_setup
assign new_final_data_read_Qual[tid] = threads_serviced_Qual[tid] ? new_final_data_read[tid] : final_data_read[tid];
end
endgenerate
assign detect_bank_miss = (valid_per_bank & ~hit_per_bank);
@@ -293,8 +295,7 @@ module VX_d_cache
genvar bank_id;
generate
for (bank_id = 0; bank_id < CACHE_BANKS; bank_id = bank_id + 1)
begin
for (bank_id = 0; bank_id < CACHE_BANKS; bank_id = bank_id + 1) begin : cache_banks
wire[31:0] bank_addr = (state == SEND_MEM_REQ) ? miss_addr :
(state == RECIV_MEM_RSP) ? miss_addr :
i_p_addr[send_index_to_bank[bank_id]];

16
rtl/cache/VX_d_cache_encapsulate.v vendored
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@@ -65,27 +65,25 @@ module VX_d_cache_encapsulate (
wire[NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata_inter;
genvar curr_thraed;
for (curr_thraed = 0; curr_thraed < `NT; curr_thraed = curr_thraed + 1) begin
genvar curr_thraed, curr_bank, curr_word;
generate
for (curr_thraed = 0; curr_thraed < `NT; curr_thraed = curr_thraed + 1) begin : threads
assign i_p_valid_inter[curr_thraed] = i_p_valid[curr_thraed];
assign i_p_addr_inter[curr_thraed] = i_p_addr[curr_thraed];
assign i_p_writedata_inter[curr_thraed] = i_p_writedata[curr_thraed];
assign o_p_readdata[curr_thraed] = o_p_readdata_inter[curr_thraed];
assign o_p_readdata_valid[curr_thraed] = o_p_readdata_valid_inter[curr_thraed];
end
genvar curr_bank;
genvar curr_word;
for (curr_bank = 0; curr_bank < NUMBER_BANKS; curr_bank = curr_bank + 1) begin
for (curr_word = 0; curr_word < `NUM_WORDS_PER_BLOCK; curr_word = curr_word + 1) begin
for (curr_bank = 0; curr_bank < NUMBER_BANKS; curr_bank = curr_bank + 1) begin : banks
for (curr_word = 0; curr_word < `NUM_WORDS_PER_BLOCK; curr_word = curr_word + 1) begin : words
assign o_m_writedata[curr_bank][curr_word] = o_m_writedata_inter[curr_bank][curr_word];
assign i_m_readdata_inter[curr_bank][curr_word] = i_m_readdata[curr_bank][curr_word];
end
end
endgenerate
VX_d_cache dcache(
.clk (clk),

1566
rtl/quartus/VX_gpr_syn.qsf
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File diff suppressed because it is too large Load Diff

27
rtl/quartus/make_pins_virtual.tcl Normal file
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@@ -0,0 +1,27 @@
load_package flow
package require cmdline
proc make_all_pins_virtual { args } {
remove_all_instance_assignments -name VIRTUAL_PIN
execute_module -tool map
set name_ids [get_names -filter * -node_type pin]
foreach_in_collection name_id $name_ids {
set pin_name [get_name_info -info full_path $name_id]
if { -1 == [lsearch -exact { clk, reset } $pin_name] } {
post_message "Making VIRTUAL_PIN assignment to $pin_name"
set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
} else {
post_message "Skipping VIRTUAL_PIN assignment to $pin_name"
}
}
export_assignments
}
make_all_pins_virtual

8
rtl/shared_memory/VX_priority_encoder_sm.v
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@@ -48,8 +48,7 @@ module VX_priority_encoder_sm
genvar curr_bank;
generate
for (curr_bank = 0; curr_bank <= NB; curr_bank = curr_bank + 1)
begin
for (curr_bank = 0; curr_bank <= NB; curr_bank = curr_bank + 1) begin : countones_blocks
wire[`CLOG2(`NT):0] num_valids;
VX_countones #(.N(`NT)) valids_counter (
@@ -71,8 +70,8 @@ module VX_priority_encoder_sm
// There's one or less valid per bank
genvar curr_bank_o;
for (curr_bank_o = 0; curr_bank_o <= NB; curr_bank_o = curr_bank_o + 1)
begin
generate
for (curr_bank_o = 0; curr_bank_o <= NB; curr_bank_o = curr_bank_o + 1) begin : encoders
VX_generic_priority_encoder #(.N(NUM_REQ)) vx_priority_encoder(
.valids(bank_valids[curr_bank_o]),
@@ -82,6 +81,7 @@ module VX_priority_encoder_sm
assign out_address[curr_bank_o] = internal_out_valid[curr_bank_o] ? in_address[internal_req_num[curr_bank_o]] : 0;
assign out_data[curr_bank_o] = internal_out_valid[curr_bank_o] ? in_data[internal_req_num[curr_bank_o]] : 0;
end
endgenerate
integer curr_b;
always @(*) begin

4
rtl/shared_memory/VX_shared_memory.v
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@@ -61,7 +61,7 @@ wire [`NT_M1:0] orig_in_valid;
genvar f;
generate
for(f = 0; f < `NT; f = f+1) begin
for(f = 0; f < `NT; f = f+1) begin : orig_in_valid_setup
assign orig_in_valid[f] = in_valid[f];
end
@@ -92,7 +92,7 @@ genvar j;
integer i;
generate
//for(j=0; j<= NB; j=j+1) begin : sm_mem_block
for(j=0; j<= SM_BANKS - 1; j=j+1) begin
for(j=0; j<= SM_BANKS - 1; j=j+1) begin : shared_mem_blocks
wire shm_write = (mem_write != `NO_MEM_WRITE) && temp_in_valid[j];