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  • 5a5c9f3981 merging changes from OPAE branch making this branch Blaise Tine 2020-03-27 20:19:16 -04:00
  • 9b1b8789ac merging changes from OPAE branch making this branch Blaise Tine 2020-03-27 20:19:16 -04:00
  • 614797e52f Migrating fpga_synthesis_temp to main felsabbagh3 2020-03-27 13:15:23 -07:00
  • 39516a6f98 Migrating fpga_synthesis_temp to main felsabbagh3 2020-03-27 13:15:23 -07:00
  • 6dc3d0d371 refactor VX_define.v Blaise Tine 2020-03-27 13:56:16 -04:00
  • d54ba1e9ae refactor VX_define.v Blaise Tine 2020-03-27 13:56:16 -04:00
  • 3df21b6e71 fixed regression bug with Vortex.v model hanging issue Blaise Tine 2020-03-27 13:19:11 -04:00
  • 4eb8769423 fixed regression bug with Vortex.v model hanging issue Blaise Tine 2020-03-27 13:19:11 -04:00
  • 985b01cb99 adding back build_config target dependency Blaise Tine 2020-03-27 12:41:03 -04:00
  • 073173067f adding back build_config target dependency Blaise Tine 2020-03-27 12:41:03 -04:00
  • 8763adf7bc update Blaise Tine 2020-03-26 04:19:53 -04:00
  • 50829e522b update Blaise Tine 2020-03-26 04:19:53 -04:00
  • a82dd9387d refactoring RTL simulator and Makefile Blaise Tine 2020-03-26 04:14:36 -04:00
  • 3252d52694 refactoring RTL simulator and Makefile Blaise Tine 2020-03-26 04:14:36 -04:00
  • 3b74f071a7 Generate define overrides based on env vars for C and Verilog. wgulian3 2020-03-26 04:05:23 -04:00
  • f126a23114 Generate define overrides based on env vars for C and Verilog. wgulian3 2020-03-26 04:05:23 -04:00
  • 33d8c507df Remove VX_define.h and *_synth and runtime/config.h wgulian3 2020-03-26 00:03:50 -04:00
  • 123fb17723 Remove VX_define.h and *_synth and runtime/config.h wgulian3 2020-03-26 00:03:50 -04:00
  • 8fd742edd8 fixed Modelsim build errors Blaise Tine 2020-03-26 03:56:44 -04:00
  • acafcceb94 fixed Modelsim build errors Blaise Tine 2020-03-26 03:56:44 -04:00
  • 9621acff5b fixed Modelsim build errors Blaise Tine 2020-03-26 03:54:23 -04:00
  • 8aa2d74714 fixed Modelsim build errors Blaise Tine 2020-03-26 03:54:23 -04:00
  • a7eb9a0c38 code refactoring Blaise Tine 2020-03-26 03:20:46 -04:00
  • 07c52d8729 code refactoring Blaise Tine 2020-03-26 03:20:46 -04:00
  • 4626389ee2 code refactoring Blaise Tine 2020-03-26 01:41:01 -04:00
  • bf3d1fb5a2 code refactoring Blaise Tine 2020-03-26 01:41:01 -04:00
  • 4e6de0dc38 Fixed most of the cache issues, mat_add left felsabbagh3 2020-03-22 15:59:45 -07:00
  • 5372c07b01 Fixed most of the cache issues, mat_add left felsabbagh3 2020-03-22 15:59:45 -07:00
  • d146070275 Fix for Single-Threaded felsabbagh3 2020-03-22 14:44:46 -07:00
  • 82ea79c680 Fix for Single-Threaded felsabbagh3 2020-03-22 14:44:46 -07:00
  • 902aa685b1 Add threaded -O3 build mode wgulian3 2020-03-20 18:15:49 -04:00
  • 10ebfd7e24 Add threaded -O3 build mode wgulian3 2020-03-20 18:15:49 -04:00
  • 1c82f9a11d revert saxpy change and fix stage_1_cycles not working wgulian3 2020-03-20 04:49:02 -04:00
  • f565d47844 revert saxpy change and fix stage_1_cycles not working wgulian3 2020-03-20 04:49:02 -04:00
  • 05b7ffff12 Add modified RTL files for parameterized builds with VX_define_synth.v wgulian3 2020-03-20 04:04:15 -04:00
  • 5b3df797a4 Add modified RTL files for parameterized builds with VX_define_synth.v wgulian3 2020-03-20 04:04:15 -04:00
  • f034b4c63a driver update Blaise Tine 2020-03-16 18:13:58 -04:00
  • 55e2cb4a76 driver test kernel Blaise Tine 2020-03-16 17:49:24 -04:00
  • 8b4397f0ec fixed runtime Makefile Blaise Tine 2020-03-16 14:58:02 -04:00
  • db87f0184b added driver sim Blaise Tine 2020-03-16 08:02:57 -04:00
  • c41855ee42 added driver sim Blaise Tine 2020-03-16 08:02:23 -04:00
  • 65f3ced608 Fixed no L3 Verilator issues felsabbagh3 2020-03-13 15:11:20 -07:00
  • ff2fc5fa43 Fixed no L3 Verilator issues felsabbagh3 2020-03-13 15:11:20 -07:00
  • fc94168e32 Removed L3 for synthesis felsabbagh3 2020-03-13 15:01:46 -07:00
  • 0f5528a229 Removed L3 for synthesis felsabbagh3 2020-03-13 15:01:46 -07:00
  • dd2c9cd9d7 Add power analysis Make target wgulian3 2020-03-12 13:14:50 -04:00
  • 07ed4085ae Add power analysis Make target wgulian3 2020-03-12 13:14:50 -04:00
  • b1e77bec44 replace procedural continuous assignments and force MLAB inference for generic_queue_ll wgulian3 2020-03-10 17:46:48 -04:00
  • c5fe43724e replace procedural continuous assignments and force MLAB inference for generic_queue_ll wgulian3 2020-03-10 17:46:48 -04:00
  • 372a1ad905 minor tweaks to appease quartus re-add fancy timing analysis scripts and revert to Makefile with custom quartus location support wgulian3 2020-03-10 04:05:01 -04:00
  • a931b588c2 minor tweaks to appease quartus re-add fancy timing analysis scripts and revert to Makefile with custom quartus location support wgulian3 2020-03-10 04:05:01 -04:00
  • 13c6cbfa5d L3 and CLUSTRING WORKS felsabbagh3 2020-03-10 02:41:47 -07:00
  • ca62e57a0d L3 and CLUSTRING WORKS felsabbagh3 2020-03-10 02:41:47 -07:00
  • cf0173ae15 Fixed Stall Pipeline Logic felsabbagh3 2020-03-09 22:08:46 -07:00
  • dea271eb6b Fixed Stall Pipeline Logic felsabbagh3 2020-03-09 22:08:46 -07:00
  • 36547821fc temp files cleanup Blaise Tine 2020-03-09 10:18:11 -04:00
  • 717a75ade8 fixed opencl benchmarks Blaise Tine 2020-03-09 09:55:16 -04:00
  • e2ffbcf14b MULTICORE WITH L2 WORKING felsabbagh3 2020-03-09 01:17:11 -07:00
  • 469334f23e MULTICORE WITH L2 WORKING felsabbagh3 2020-03-09 01:17:11 -07:00
  • a539630a0a Added Vortex SOC felsabbagh3 2020-03-08 15:24:21 -07:00
  • 24f20a2da4 Added Vortex SOC felsabbagh3 2020-03-08 15:24:21 -07:00
  • b5b04a7070 Added Shared Memory felsabbagh3 2020-03-08 15:00:53 -07:00
  • 6c52b3d09b Added Shared Memory felsabbagh3 2020-03-08 15:00:53 -07:00
  • b9a95631bc Icache stage mods + removed shared memory felsabbagh3 2020-03-08 14:04:55 -07:00
  • ec1aad1591 Icache stage mods + removed shared memory felsabbagh3 2020-03-08 14:04:55 -07:00
  • 2f94b26af0 Icache working felsabbagh3 2020-03-08 13:59:35 -07:00
  • f315a8a44d Icache working felsabbagh3 2020-03-08 13:59:35 -07:00
  • 507d20f413 Cache Working on Mem Copy felsabbagh3 2020-03-08 01:55:15 -08:00
  • 3b11e1d72f Cache Working on Mem Copy felsabbagh3 2020-03-08 01:55:15 -08:00
  • f03f3fe037 Fixed all Cache Warnings felsabbagh3 2020-03-07 14:34:05 -08:00
  • 4ed62f1aad Fixed all Cache Warnings felsabbagh3 2020-03-07 14:34:05 -08:00
  • 3953a71180 fixed write logic in generic_queue_ll Blaise Tine 2020-03-07 06:56:11 -05:00
  • ddafe96ca6 fixed write logic in generic_queue_ll Blaise Tine 2020-03-07 06:56:11 -05:00
  • 9bf0add937 Made the cache module configurable for multi-instantiation felsabbagh3 2020-03-07 00:49:40 -08:00
  • db11bf6990 Made the cache module configurable for multi-instantiation felsabbagh3 2020-03-07 00:49:40 -08:00
  • fb23812e95 Added Lower Level Cache Hit Queue felsabbagh3 2020-03-06 23:04:42 -08:00
  • 90d10f4b7d Added Lower Level Cache Hit Queue felsabbagh3 2020-03-06 23:04:42 -08:00
  • 44f6c68fe9 Got queue_ll to work by modifying when to update bypass felsabbagh3 2020-03-06 22:50:20 -08:00
  • 2c616d8201 Got queue_ll to work by modifying when to update bypass felsabbagh3 2020-03-06 22:50:20 -08:00
  • 0816426662 added unit_test Blaise Tine 2020-03-06 10:31:31 -05:00
  • abfd592fd2 added unit_test Blaise Tine 2020-03-06 10:31:31 -05:00
  • 9f5235dc3d added generic_queue_ll Blaise Tine 2020-03-05 10:43:15 -05:00
  • 730c36ef18 added generic_queue_ll Blaise Tine 2020-03-05 10:43:15 -05:00
  • 9c56a10f15 synthesis fixes Blaise Tine 2020-03-05 09:11:43 -05:00
  • 721d22ae86 synthesis fixes Blaise Tine 2020-03-05 09:11:43 -05:00
  • 33868512ac synthesis fixes Blaise Tine 2020-03-05 07:03:23 -05:00
  • 2ed98a4764 synthesis fixes Blaise Tine 2020-03-05 07:03:23 -05:00
  • 66a46f81ce synthesis fixes Blaise Tine 2020-03-05 06:58:51 -05:00
  • 369c2c625c synthesis fixes Blaise Tine 2020-03-05 06:58:51 -05:00
  • 457e8644f3 Added Snoop Invalidate/Writeback Req type felsabbagh3 2020-03-05 01:30:16 -08:00
  • 7222cdd199 Added Snoop Invalidate/Writeback Req type felsabbagh3 2020-03-05 01:30:16 -08:00
  • e0620a6f6a Added fill_invalidator felsabbagh3 2020-03-04 23:55:02 -08:00
  • c257c0578e Added fill_invalidator felsabbagh3 2020-03-04 23:55:02 -08:00
  • b038bdb491 New Cache Design Passing All Tests felsabbagh3 2020-03-04 23:24:32 -08:00
  • a86a403ca9 New Cache Design Passing All Tests felsabbagh3 2020-03-04 23:24:32 -08:00
  • b0b9b8238e Passing some cases felsabbagh3 2020-03-04 04:05:54 -08:00
  • aa1a0ee376 Passing some cases felsabbagh3 2020-03-04 04:05:54 -08:00
  • 8f001ac6f2 Added All Interfaces felsabbagh3 2020-03-03 22:48:49 -08:00
  • d8e25045be Added All Interfaces felsabbagh3 2020-03-03 22:48:49 -08:00
  • 73cecd3866 Added Core Interface felsabbagh3 2020-03-03 22:14:56 -08:00