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Added Lower Level Cache Hit Queue

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This commit is contained in:
felsabbagh3
2020-03-06 23:04:42 -08:00
parent 44f6c68fe9
commit fb23812e95
5 changed files with 122 additions and 3 deletions
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31
rtl/VX_cache/VX_bank.v
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@@ -46,7 +46,14 @@ module VX_bank (
// Snp Request
input wire snp_req,
input wire[31:0] snp_req_addr
input wire[31:0] snp_req_addr,
// Lower Level Cache Response
input wire llvq_pop,
output wire llvq_valid,
output wire[31:0] llvq_res_addr,
output wire[`BANK_LINE_SIZE_RNG][31:0] llvq_res_data,
output wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] llvq_res_tid
);
@@ -439,6 +446,28 @@ module VX_bank (
);
// Lower Cache Hit
wire llvq_empty;
wire llvq_full;
wire llvq_push = valid_st2 && !miss_st2;
wire[`BANK_LINE_SIZE_RNG][31:0] llvq_push_data = readdata_st2;
wire llvq_addr = addr_st2;
wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] llvq_tid = miss_add_tid;
assign llvq_valid = !llvq_empty;
VX_generic_queue_ll #(.DATAW(`vx_clog2(`NUMBER_REQUESTS) + 32 + (`BANK_LINE_SIZE_WORDS * 32)), .SIZE(`LLVQ_SIZE)) llv_queue(
.clk (clk),
.reset (reset),
.push (llvq_push),
.in_data ({llvq_tid , llvq_addr , llvq_push_data}),
.pop (llvq_pop),
.out_data({llvq_res_tid, llvq_res_addr, llvq_res_data}),
.empty (llvq_empty),
.full (llvq_full)
);
assign stall_bank_pipe = (cwbq_push && cwbq_full) || (dwbq_push && dwbq_full) || (miss_add && mrvq_full) || (dram_fill_req && dram_fill_req_queue_full);
endmodule

51
rtl/VX_cache/VX_cache.v
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@@ -45,7 +45,13 @@ module VX_cache (
// Snoop Req
input wire snp_req,
input wire[31:0] snp_req_addr
input wire[31:0] snp_req_addr,
// Lower Level Cache
input wire llvq_pop,
output wire[`NUMBER_REQUESTS-1:0] llvq_valid,
output wire[`NUMBER_REQUESTS-1:0][31:0] llvq_res_addr,
output wire[`NUMBER_REQUESTS-1:0][`BANK_LINE_SIZE_RNG][31:0] llvq_res_data
);
@@ -73,11 +79,31 @@ module VX_cache (
wire[`NUMBER_BANKS-1:0] per_bank_reqq_full;
wire[`NUMBER_BANKS-1:0] per_bank_llvq_pop;
wire[`NUMBER_BANKS-1:0] per_bank_llvq_valid;
wire[`NUMBER_BANKS-1:0][31:0] per_bank_llvq_res_addr;
wire[`NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][31:0] per_bank_llvq_res_data;
wire [`NUMBER_BANKS-1:0][`vx_clog2(`NUMBER_REQUESTS)-1:0] per_bank_llvq_res_tid;
assign delay_req = (|per_bank_reqq_full);
assign dram_fill_accept = (`NUMBER_BANKS == 1) ? per_bank_dram_fill_accept[0] : per_bank_dram_fill_accept[dram_fill_rsp_addr[`BANK_SELECT_ADDR_RNG]];
VX_dcache_llv_resp_bank_sel VX_dcache_llv_resp_bank_sel(
.per_bank_llvq_pop (per_bank_llvq_pop),
.per_bank_llvq_valid (per_bank_llvq_valid),
.per_bank_llvq_res_addr(per_bank_llvq_res_addr),
.per_bank_llvq_res_data(per_bank_llvq_res_data),
.per_bank_llvq_res_tid (per_bank_llvq_res_tid),
.llvq_pop (llvq_pop),
.llvq_valid (llvq_valid),
.llvq_res_addr (llvq_res_addr),
.llvq_res_data (llvq_res_data)
);
VX_cache_dram_req_arb VX_cache_dram_req_arb(
.clk (clk),
.reset (reset),
@@ -164,6 +190,14 @@ module VX_cache (
wire curr_bank_reqq_full;
wire curr_bank_llvq_pop;
wire curr_bank_llvq_valid;
wire[31:0] curr_bank_llvq_res_addr;
wire[`BANK_LINE_SIZE_RNG][31:0] curr_bank_llvq_res_data;
wire[`vx_clog2(`NUMBER_REQUESTS)-1:0] curr_bank_llvq_res_tid;
// Core Req
assign curr_bank_valids = per_bank_valids[curr_bank];
assign curr_bank_addr = core_req_addr;
@@ -207,6 +241,13 @@ module VX_cache (
assign curr_bank_snp_req_addr = snp_req_addr;
// LLVQ
assign curr_bank_llvq_pop = per_bank_llvq_pop[curr_bank];
assign per_bank_llvq_valid[curr_bank] = curr_bank_llvq_valid;
assign per_bank_llvq_res_data[curr_bank] = curr_bank_llvq_res_data;
assign per_bank_llvq_res_addr[curr_bank] = curr_bank_llvq_res_addr;
assign per_bank_llvq_res_tid[curr_bank] = curr_bank_llvq_res_tid;
VX_bank bank (
.clk (clk),
.reset (reset),
@@ -252,7 +293,13 @@ module VX_cache (
// Snoop Request
.snp_req (curr_bank_snp_req),
.snp_req_addr (curr_bank_snp_req_addr)
.snp_req_addr (curr_bank_snp_req_addr),
.llvq_pop (curr_bank_llvq_pop),
.llvq_valid (curr_bank_llvq_valid),
.llvq_res_addr (curr_bank_llvq_res_addr),
.llvq_res_data (curr_bank_llvq_res_data),
.llvq_res_tid (curr_bank_llvq_res_tid)
);
end

2
rtl/VX_cache/VX_cache_config.v
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@@ -37,6 +37,8 @@
`define DWBQ_SIZE 4
// Dram Fill Req Queue Size
`define DFQQ_SIZE `REQQ_SIZE
// Lower Level Cache Hit Queue Size
`define LLVQ_SIZE 16
// Fill Invalidator Active {Comment out define statement to invalidate}
`define FILL_INVALIDATOR_ACTIVE 1

41
rtl/VX_cache/VX_dcache_llv_resp_bank_sel.v Normal file
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@@ -0,0 +1,41 @@
`include "VX_cache_config.v"
module VX_dcache_llv_resp_bank_sel (
output reg [`NUMBER_BANKS-1:0] per_bank_llvq_pop,
input wire[`NUMBER_BANKS-1:0] per_bank_llvq_valid,
input wire[`NUMBER_BANKS-1:0][31:0] per_bank_llvq_res_addr,
input wire[`NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][31:0] per_bank_llvq_res_data,
input wire[`NUMBER_BANKS-1:0][`vx_clog2(`NUMBER_REQUESTS)-1:0] per_bank_llvq_res_tid,
input wire llvq_pop,
output reg[`NUMBER_REQUESTS-1:0] llvq_valid,
output reg[`NUMBER_REQUESTS-1:0][31:0] llvq_res_addr,
output reg[`NUMBER_REQUESTS-1:0][`BANK_LINE_SIZE_RNG][31:0] llvq_res_data
);
wire [(`vx_clog2(`NUMBER_BANKS))-1:0] main_bank_index;
wire found_bank;
VX_generic_priority_encoder #(.N(`NUMBER_BANKS)) VX_sel_bank(
.valids(per_bank_llvq_valid),
.index (main_bank_index),
.found (found_bank)
);
always @(*) begin
llvq_valid = 0;
llvq_res_addr = 0;
llvq_res_data = 0;
per_bank_llvq_pop = 0;
if (found_bank && llvq_pop) begin
llvq_valid [per_bank_llvq_res_tid] = 1;
llvq_res_addr[per_bank_llvq_res_tid] = per_bank_llvq_res_addr[main_bank_index];
llvq_res_data[per_bank_llvq_res_tid] = per_bank_llvq_res_data[main_bank_index];
per_bank_llvq_pop[main_bank_index] = 1;
end
end
endmodule

0
rtl/results.txt
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