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synthesis fixes

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This commit is contained in:
Blaise Tine
2020-03-05 09:11:43 -05:00
parent 33868512ac
commit 9c56a10f15
8 changed files with 10 additions and 37 deletions
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2
rtl/VX_cache/VX_cache_core_req_bank_sel.v
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@@ -1,4 +1,6 @@
`include "VX_cache_config.v"
module VX_cache_core_req_bank_sel (
input wire [`NUMBER_REQUESTS-1:0] core_req_valid,
input wire [`NUMBER_REQUESTS-1:0][31:0] core_req_addr,

13
rtl/VX_cache/VX_fill_invalidator.v
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@@ -1,4 +1,3 @@
`include "VX_cache_config.v"
module VX_fill_invalidator (
@@ -30,19 +29,19 @@ module VX_fill_invalidator (
integer curr_fill;
always @(*) begin
assign invalidate_fill = 0;
assign success_found = 0;
assign success_index = 0;
invalidate_fill = 0;
success_found = 0;
success_index = 0;
for (curr_fill = 0; curr_fill < `FILL_INVALIDAOR_SIZE; curr_fill=curr_fill+1) begin
if (fill_addr[31:`LINE_SELECT_ADDR_START] == fills_address[curr_fill][31:`LINE_SELECT_ADDR_START]) begin
if (possible_fill && fills_active[curr_fill]) begin
assign invalidate_fill = 1;
invalidate_fill = 1;
end
if (success_fill) begin
assign success_found = 1;
assign success_index = curr_fill;
success_found = 1;
success_index = curr_fill;
end
end
end

2
rtl/VX_cache/VX_tag_data_structure.v
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@@ -1,3 +1,5 @@
`include "VX_cache_config.v"
module VX_tag_data_structure (
input wire clk,
input wire reset,

1
rtl/quartus/fit.chg
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@@ -1 +0,0 @@
done

1
rtl/quartus/map.chg
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@@ -1 +0,0 @@
Thu Mar 05 06:08:03 2020

26
rtl/quartus/smart.log
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@@ -1,26 +0,0 @@
Info: *******************************************************************
Info: Running Quartus Prime Shell
Info: Version 18.0.0 Build 219 04/25/2018 SJ Pro Edition
Info: Copyright (C) 2018 Intel Corporation. All rights reserved.
Info: Your use of Intel Corporation's design tools, logic functions
Info: and other software and tools, and its AMPP partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel FPGA IP License Agreement, or other applicable license
Info: agreement, including, without limitation, that your use is for
Info: the sole purpose of programming logic devices manufactured by
Info: Intel and sold by Intel or its authorized distributors. Please
Info: refer to the applicable agreement for further details.
Info: Processing started: Thu Mar 5 06:08:03 2020
Info: Command: quartus_sh --determine_smart_action Vortex
Info: Quartus(args): Vortex
Info: SMART_ACTION = SOURCE
Info (23030): Evaluation of Tcl script /tools/reconfig/intel/18.0/quartus/common/tcl/internal/qsh_smart.tcl was successful
Info: Quartus Prime Shell was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 689 megabytes
Info: Processing ended: Thu Mar 5 06:08:04 2020
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01

1
rtl/quartus/sta.chg
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@@ -1 +0,0 @@
done

1
rtl/quartus/syn.chg
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@@ -1 +0,0 @@
done