felsabbagh3
313a8e3b4b
All cache bugs fixed - Handshaking
2020-03-28 21:43:02 -07:00
felsabbagh3
5dc9493c61
ALL tests passing - handshake
2020-03-27 21:34:49 -07:00
Blaise Tine
f7e0d1e491
missing runtime changes from OPAE
2020-03-27 22:51:54 -04:00
Blaise Tine
89d5bfbef1
missing simX changes from OPAE
2020-03-27 22:44:16 -04:00
Blaise Tine
e80fa7f233
missing rtl changes from OPAE
2020-03-27 22:37:35 -04:00
Blaise Tine
550d96a73c
rtlsim driver works with Vortex!
2020-03-27 21:54:55 -04:00
Blaise Tine
5d320a9313
fixed multicore build
2020-03-27 21:04:23 -04:00
Blaise Tine
51fd8974a9
minor build fixes
2020-03-27 20:56:18 -04:00
Blaise Tine
5a5c9f3981
merging changes from OPAE branch making this branch
2020-03-27 20:19:16 -04:00
felsabbagh3
614797e52f
Migrating fpga_synthesis_temp to main
2020-03-27 13:15:23 -07:00
Blaise Tine
6dc3d0d371
refactor VX_define.v
2020-03-27 13:56:16 -04:00
Blaise Tine
3df21b6e71
fixed regression bug with Vortex.v model hanging issue
2020-03-27 13:19:11 -04:00
Blaise Tine
985b01cb99
adding back build_config target dependency
2020-03-27 12:41:03 -04:00
Blaise Tine
8763adf7bc
update
2020-03-26 04:19:53 -04:00
Blaise Tine
a82dd9387d
refactoring RTL simulator and Makefile
2020-03-26 04:14:36 -04:00
wgulian3
3b74f071a7
Generate define overrides based on env vars for C and Verilog.
...
gen_config.py has two main jobs. First it parses env vars for anything starting with V_ and treats this as an override define. These defines are inserted into the emitted .h and .v headers with correct syntax for C and Verilog preprocessors, respectively. Second, it translates VX_define.v including all conditional definition rules into a C header. This way, all values defined in VX_define.v can also be referenced in corresponding runtime or Verilator code.
2020-03-26 04:08:43 -04:00
wgulian3
33d8c507df
Remove VX_define.h and *_synth and runtime/config.h
2020-03-26 04:07:17 -04:00
Blaise Tine
8fd742edd8
fixed Modelsim build errors
2020-03-26 03:56:44 -04:00
Blaise Tine
9621acff5b
fixed Modelsim build errors
2020-03-26 03:54:23 -04:00
Blaise Tine
a7eb9a0c38
code refactoring
2020-03-26 03:20:46 -04:00
Blaise Tine
4626389ee2
code refactoring
2020-03-26 01:41:01 -04:00
felsabbagh3
4e6de0dc38
Fixed most of the cache issues, mat_add left
2020-03-22 15:59:45 -07:00
felsabbagh3
d146070275
Fix for Single-Threaded
2020-03-22 14:44:46 -07:00
wgulian3
902aa685b1
Add threaded -O3 build mode
2020-03-21 17:23:40 -04:00
wgulian3
1c82f9a11d
revert saxpy change and fix stage_1_cycles not working
2020-03-20 04:49:02 -04:00
wgulian3
05b7ffff12
Add modified RTL files for parameterized builds with VX_define_synth.v
2020-03-20 04:04:15 -04:00
felsabbagh3
65f3ced608
Fixed no L3 Verilator issues
2020-03-13 15:11:20 -07:00
felsabbagh3
fc94168e32
Removed L3 for synthesis
2020-03-13 15:01:46 -07:00
wgulian3
dd2c9cd9d7
Add power analysis Make target
2020-03-12 13:14:50 -04:00
wgulian3
b1e77bec44
replace procedural continuous assignments and force MLAB inference for generic_queue_ll
2020-03-10 17:46:48 -04:00
wgulian3
372a1ad905
minor tweaks to appease quartus
...
re-add fancy timing analysis scripts and revert to Makefile with custom quartus location support
2020-03-10 12:15:30 -04:00
felsabbagh3
13c6cbfa5d
L3 and CLUSTRING WORKS
2020-03-10 02:41:47 -07:00
felsabbagh3
cf0173ae15
Fixed Stall Pipeline Logic
2020-03-09 22:08:46 -07:00
felsabbagh3
e2ffbcf14b
MULTICORE WITH L2 WORKING
2020-03-09 01:17:11 -07:00
felsabbagh3
a539630a0a
Added Vortex SOC
2020-03-08 15:24:21 -07:00
felsabbagh3
b5b04a7070
Added Shared Memory
2020-03-08 15:00:53 -07:00
felsabbagh3
b9a95631bc
Icache stage mods + removed shared memory
2020-03-08 14:04:55 -07:00
felsabbagh3
2f94b26af0
Icache working
2020-03-08 13:59:35 -07:00
felsabbagh3
507d20f413
Cache Working on Mem Copy
2020-03-08 01:55:15 -08:00
felsabbagh3
f03f3fe037
Fixed all Cache Warnings
2020-03-07 14:34:05 -08:00
Blaise Tine
3953a71180
fixed write logic in generic_queue_ll
2020-03-07 06:56:11 -05:00
felsabbagh3
9bf0add937
Made the cache module configurable for multi-instantiation
2020-03-07 00:49:40 -08:00
felsabbagh3
fb23812e95
Added Lower Level Cache Hit Queue
2020-03-06 23:04:42 -08:00
felsabbagh3
44f6c68fe9
Got queue_ll to work by modifying when to update bypass
2020-03-06 22:50:20 -08:00
Blaise Tine
0816426662
added unit_test
2020-03-06 10:31:31 -05:00
Blaise Tine
9f5235dc3d
added generic_queue_ll
2020-03-05 10:43:15 -05:00
Blaise Tine
9c56a10f15
synthesis fixes
2020-03-05 09:11:43 -05:00
Blaise Tine
33868512ac
synthesis fixes
2020-03-05 07:03:23 -05:00
Blaise Tine
66a46f81ce
synthesis fixes
2020-03-05 06:58:51 -05:00
felsabbagh3
457e8644f3
Added Snoop Invalidate/Writeback Req type
2020-03-05 01:30:16 -08:00
