Zitao Fang
0c8771c35e
Merge branch 'dev' of github.com:ucb-bar/chipyard into sodor-integrate
2020-09-18 22:33:42 -07:00
Zitao Fang
a43400acb9
Update CI
2020-09-18 15:36:33 -07:00
Jerry Zhao
ba05b32f9c
Merge pull request #673 from ucb-bar/serial-tl
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Serial-tilelink backing memory
2020-09-18 15:30:04 -07:00
Jerry Zhao
382cefcee0
Merge pull request #89 from ucb-bar/support-plusargs
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Support plusarg_reader in TestHarness | explicitly name generated IOs
2020-09-18 13:28:31 -07:00
David Biancolin
f36183d236
[clocks] Update AssignerKey name and comment
2020-09-18 11:28:31 -07:00
Jerry Zhao
bbf941c865
Bump Firesim
2020-09-18 10:43:58 -07:00
Jerry Zhao
aa355c7c1a
Bump firesim
2020-09-18 10:41:59 -07:00
Jerry Zhao
b9622c5132
Merge remote-tracking branch 'origin/dev' into serial-tl
2020-09-18 01:00:13 -07:00
James Dunn
9135cda959
Bypassing AON for system.reset. Using reset_core in ArtyShell test harness, which is derived from Xilinx reset IP block's mb_reset. Changing dutReset to same reset_core.
2020-09-17 13:43:28 -07:00
Jerry Zhao
4a5c75fcf8
Add explicit naming of IOs generated by generateIOFromSignal
2020-09-17 13:21:32 -07:00
David Biancolin
ad147ec7f2
[clocks] Remove dealiaser and node injector until they are needed
2020-09-17 11:43:39 -07:00
David Biancolin
0f33ea3999
[clocks] Stringly specified clock frequencies; DRY out schemes
2020-09-17 11:41:05 -07:00
David Biancolin
6a26a350ee
[clocks] Update dealiaser based on feedback
2020-09-17 11:33:26 -07:00
David Biancolin
cfa7e30d95
[clocks] Fix comment in ClockDividerN
2020-09-17 11:32:51 -07:00
Jerry Zhao
43f746edb6
Merge pull request #675 from ucb-bar/faster-ci
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Improve CI build times by grouping similar builds
2020-09-16 22:55:27 -07:00
David Biancolin
b8d3e4a66d
Update Idealized PLL config
2020-09-16 16:30:25 -07:00
David Biancolin
8e4dedcecf
Remove require guard on divided configs
2020-09-16 16:30:00 -07:00
David Biancolin
895bacea98
WIP - Simple divider-only PLL generation flow
2020-09-16 16:00:26 -07:00
Jerry Zhao
6874308981
Address review comments
2020-09-16 15:43:25 -07:00
Jerry Zhao
269af01a70
Bump testchipip
2020-09-16 13:51:33 -07:00
Jerry Zhao
36ccb12560
Bump testchipip
2020-09-16 10:29:03 -07:00
Jerry Zhao
aa8b7c15ec
Reduce CI redundancy by grouping builds
2020-09-16 00:57:05 -07:00
abejgonzalez
f1b40d51af
Connected clocks | Exposed Master TL port
2020-09-15 12:58:58 -07:00
Zitao Fang
1543acfacd
Merge branch 'dev' of github.com:ucb-bar/chipyard into sodor-integrate
2020-09-14 23:55:05 -07:00
Zitao Fang
642441e0a2
Replaced memory and fixed 3-stage single port arbiter
2020-09-14 23:54:52 -07:00
Jerry Zhao
0d8e87126c
Deprecate support for on-chip SerialAdapter
2020-09-14 19:43:32 -07:00
Jerry Zhao
847f72eca0
Support plusarg_reader blackbox in the harness
2020-09-14 19:39:44 -07:00
Jerry Zhao
f9cc1dc2c2
Merge remote-tracking branch 'origin/dev' into serial-tl
2020-09-14 19:35:43 -07:00
Jerry Zhao
23a199eccf
Merge pull request #674 from ucb-bar/iocells-fix
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Undo regression in iocells flexibility
2020-09-14 19:32:37 -07:00
Jerry Zhao
1435f09ce6
Merge pull request #88 from ucb-bar/iocell-fix
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Undo regression in iocell flexibility
2020-09-14 19:28:36 -07:00
Jerry Zhao
10625a3a6c
Undo regression in iocells flexibility
2020-09-14 13:27:31 -07:00
Jerry Zhao
31590a7948
Undo regression in iocell flexibility
2020-09-14 13:24:44 -07:00
Jerry Zhao
16c80112a7
Merge pull request #670 from ucb-bar/harness-refactor
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Split IOBinders into IOBinders and HarnessBinders | punch out clocks to harness for simwidgets and bridges
2020-09-14 12:45:46 -07:00
Jerry Zhao
e6e1ed85f2
Merge pull request #86 from ucb-bar/iocell-params
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Clean up IOCell types and parameterization
2020-09-14 12:00:33 -07:00
chick
d06d8cc16c
- FoundryPadsYaml would not parse yaml
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- Made separate case class for data
- Now parses
- Fails later with UnknownType in firrt compiler
- Fixed similar parsing problem with PadPlacement
2020-09-14 09:32:18 -07:00
Zitao Fang
5506f77679
Add CircleCI check and update Sodor config
2020-09-14 09:14:57 -07:00
abejgonzalez
72c0f4b3d3
Add GPIO Overlay
2020-09-13 16:37:20 -07:00
Jerry Zhao
6c5bce5430
Support Tilelink over serial
2020-09-13 11:59:16 -07:00
Jerry Zhao
be0c041232
Bump Firesim
2020-09-13 06:36:37 +00:00
Jerry Zhao
d2b42cee2c
Bump testchipip
2020-09-12 23:31:54 -07:00
abejgonzalez
69bf39bf13
Added more overlays | Closer to bringup platform
2020-09-12 18:18:13 -07:00
chick
67de39e957
Refactor tapeout for Chisel 3.4, Firrtl 1.4
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- Remove clk package based on discussion with Colin
- Annotations need to be refactored to using latest API
- Generally that involves making annos generated by a anonymous ChiselAnnotation
- The chisel annotations will use RunFirrtlTransform to queue up its associated transform
- Chisel annotation provieds toFirrtl to generate Firrtl form of annotation
- Usages of unapply on firrtl annotations cannot use generic unapply(target, transform, data) which has been eliminated
- Have transforms use with DependencyAPIMigration to avoid deprecated `form`s
- Added some 'see License comments
- TechnologyLocation section of AddIOPadsSpec does not currently run because there is no content for it.
- Added some tests for annotation serialization here
2020-09-11 17:06:19 -07:00
abejgonzalez
382e5f1ae8
Add forgotten file
2020-09-11 17:02:22 -07:00
abejgonzalez
e98a0f172f
Connected UART nicely
2020-09-11 16:55:25 -07:00
Jerry Zhao
a5385c0a54
Update testchipip/icenet to use rocket-chip Located API
2020-09-11 00:02:07 -07:00
chick
e4cd2b01fe
This is mess clean it up
2020-09-10 14:35:10 -07:00
Zitao Fang
15d53e2cda
Bump to the latest Rocket
2020-09-09 15:12:37 -07:00
Jerry Zhao
facef464e6
Update BridgeBinders | fix runtime HarnessBinder port type checks
2020-09-09 00:15:02 -07:00
Jerry Zhao
8f9574fd79
Clean up passing ports from IOBinders to HarnessBinders
2020-09-08 22:30:17 -07:00
abejgonzalez
56eead4053
NOT WORKING: VCU118 Commit
2020-09-08 17:04:56 -07:00
