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60 Commits

Author SHA1 Message Date
Colin Schmidt
db0efd38fc Fix CI tests 2020-02-19 17:23:10 -08:00
Colin Schmidt
7de4c478c3 Update to chisel 3.2.x 2020-02-18 14:56:17 -08:00
Colin Schmidt
e0081208b9 Updates for rocket-chip bump 2019-12-06 15:39:14 -08:00
Colin Schmidt
e4cce07c78 Fix issues after chisel update for august 2019 2019-12-06 15:38:19 -08:00
Abraham Gonzalez
3bba55ccc8 Merge pull request #68 from ucb-bar/print-firrtl-exception 
Print the firrtl exception if we get one
 2019-11-07 13:39:12 -08:00
Abraham Gonzalez
1e114d0355 Match inner variables 2019-11-07 10:17:24 -08:00
Colin Schmidt
c1004790cc Use x instead of e to match other case 2019-10-28 07:33:04 -07:00
Colin Schmidt
c96a5e5f44 Print the firrtl exception if we get one 
Fixes #67
 2019-10-24 14:55:03 -07:00
Albert Magyar
76ccb75b00 Filter out all deleted annotations 2019-08-19 09:08:30 -07:00
Abraham Gonzalez
76f6c8adb2 remove large annotations 2019-08-17 10:35:41 -07:00
Albert Magyar
26096e07f6 Coordinate Top and Harness generation (#63) 
* Coordinate Top and Harness generation

* Update to use .f filename override annotations

* Move top generation to def to help GC
 2019-07-30 22:42:05 -07:00
Albert Magyar
e3c822709b Filter all EmittedAnnotations from JSON emission (#64) 
* Filter all EmittedAnnotations from JSON emission

* Filter more annotations
 2019-07-29 20:39:07 -07:00
Colin Schmidt
c23b2b6f84 SRAM depth to bigint 
max synflop depth support
Fix annotation mangling on the harness side
 2019-05-14 10:10:47 -07:00
John Wright
e548210ef4 Add options to emit top/harness firrtl and annotations (#54) 2019-03-29 13:55:18 -07:00
Colin Schmidt
8f7af5b0bf Fix annos (#53) 
* Fixes #36 by using the renamemap
* Also fix harness passes annotation handling h/t azidar
* Remove old comment
 2019-03-27 17:20:41 -07:00
Colin Schmidt
fdad525007 HighForm has whens so we need to check for instances there (#49) 
Fixes a bug
 2019-03-18 11:25:58 -07:00
Colin Schmidt
6cdf978a6d Fix forms of passes to happen before replseqmem 
This ensures the conf file doesn't have any testharness
memories, which are too big and break downstream tools
 2019-03-18 07:25:04 -07:00
Colin Schmidt
a10a6cca35 Add SimDTM to list of extmodules 2019-03-01 18:52:41 -08:00
John Wright
1f58ea1e14 Style/Comments from review of #35 2019-02-13 10:15:51 -08:00
John Wright
79b8fd324b This compiles and works correctly, but is kind of hacky, and will break as soon as any additional external/blackbox modules are added to the test harness. The test harness should detect external modules and not rename them instead of what is happening here. 2019-02-13 10:15:51 -08:00
John Wright
c8efc5e88b Refactor the harness generation; use upstream arguments and passes where appropriate 2019-02-13 10:15:51 -08:00
Paul Rigge
22e6d9c5d4 Fix repl-seq-mem 2019-02-13 10:15:51 -08:00
Paul Rigge
7bbf7f00f6 Run transforms in slightly different order 
Also, don't rename TestHarness.
 2019-02-13 10:15:51 -08:00
Paul Rigge
801abd98bb Fix null pointer exception in options parser 2019-02-13 10:15:51 -08:00
Paul Rigge
f310d45381 Refactor barstools for new versions of things. 
- No handlebars (not being published for Scala 2.12)
- Update for new annotations APIs

Bump sbt-dependency-graph to 0.9.2 for this scala version
 2019-02-13 10:15:51 -08:00
Donggyu Kim
9de1f5f2c0 restructure macros for better submoduling 2017-10-03 11:56:30 -07:00
Edward Wang
607e810b1d Autogenerate almost all the depth tests 2017-10-03 11:56:30 -07:00
Edward Wang
8beb8b3f6f Don't unbox BigInt to Double 2017-10-03 11:56:30 -07:00
Edward Wang
bb2783994a Only use powers of two masks, for now 2017-10-03 11:56:30 -07:00
Edward Wang
cf0d40f658 Fix typos 2017-10-03 11:56:30 -07:00
Edward Wang
80ca2e538f Use require statement 2017-10-03 11:56:30 -07:00
Edward Wang
3cb424cf80 Add non power of two tests 2017-10-03 11:56:30 -07:00
Edward Wang
42febeb32a Rename files 2017-10-03 11:56:30 -07:00
Edward Wang
c79ea47909 Port to MDF library and start re-developing tests 2017-10-03 11:56:30 -07:00
Donggyu Kim
57b0fec78e anonymize technology 2017-10-03 11:56:30 -07:00
Donggyu Kim
aeb303a61b Colin's fixes 2017-10-03 11:56:30 -07:00
Donggyu Kim
2fd928fbe0 fix cost 2017-10-03 11:56:30 -07:00
Donggyu Kim
02fef8e2c3 graceful handling of empty files 2017-10-03 11:56:30 -07:00
Donggyu Kim
9e7c8dce3e add SynFlops 2017-10-03 11:56:30 -07:00
Donggyu Kim
4f5a9ae02e connect extra ports 2017-10-03 11:56:30 -07:00
Donggyu Kim
98155dd831 tests for macro compiler 2017-10-03 11:56:30 -07:00
Donggyu Kim
f3d39ad08f initial port attempt for macro compiler 2017-10-03 11:56:30 -07:00
Adam Izraelevitz
c5d01ba19c Added retime annotation 2017-09-06 14:44:09 -07:00
Adam Izraelevitz
96939c9ab6 Moved clkgen -> .clkgen and pads -> .pads 
They no longer compile with the latest Chisel/FIRRTL, and
may not be supported. However, future work will need them, so
this keeps the files around but are ignored by sbt.
 2017-09-06 14:44:09 -07:00
Chick Markley
16846b86fd DiGraph was being being confused with the DigGraph in firrtl. This led to pathological exceptions (#22) 
No such method error on accessing a lazy val.
InstanceGraph seemed also to be a duplicate of firrtl code
---
IOPadSpec fails no two tests but these seem to be at least an ordinary error. And should be debugged separately
 2017-04-04 10:47:59 -07:00
Angie Wang
5b5c8c82db Revert "[stevo]: add custom analog annotation" (#21) 
* Revert "[stevo]: add custom analog annotation (#20)"

This reverts commit 7ad088503f.
 2017-04-02 13:12:51 -07:00
Angie
9305dd08eb remove functionality from clkgen pass due to compatibility issue with latest firrtl 2017-04-02 04:34:38 -07:00
Angie
7c0e6c89d2 firrtl still hasn't fixed the problem with wir primops 2017-04-02 04:26:27 -07:00
Angie Wang
7ad088503f [stevo]: add custom analog annotation (#20) 2017-04-02 04:12:31 -07:00
Angie Wang
a13869b6aa Refactor repo for lastest changes to firrtl transform api changes (#19) 2017-04-02 04:10:46 -07:00