wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Colin's fixes

Browse Source
This commit is contained in:
Donggyu Kim
2017-07-21 00:27:48 -07:00
committed by edwardcwang
parent 2fd928fbe0
commit aeb303a61b
3 changed files with 15 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
tapeout/src/main/scala/transforms/macros/MacroCompiler.scala
View File

@@ -36,7 +36,7 @@ class MacroCompilerPass(mems: Option[Seq[Macro]],
for (i <- 0 until mem.width.toInt) {
if (i <= last + 1) {
/* Palmer: Every memory is going to have to fit at least a single bit. */
// coninue
// continue
} else if ((i - last) % lib.width.toInt == 0) {
/* Palmer: It's possible that we rolled over a memory's width here,
if so generate one. */
@@ -53,7 +53,7 @@ class MacroCompilerPass(mems: Option[Seq[Macro]],
case (_, None) => // continue
case (_, Some(p)) if p == lib.width => // continue
case _ =>
System.err println "Bit-mask (or unmasked) target memories are suppored only"
System.err println "Bit-mask (or unmasked) target memories are supported only"
return None
}
}
@@ -198,7 +198,7 @@ class MacroCompilerPass(mems: Option[Seq[Macro]],
* there isn't a write enable port. */
WRef(mem)
case None =>
/* Palemr: If there is no input port on the source memory port
/* Palmer: If there is no input port on the source memory port
* then we don't ever want to turn on this write
* enable. Otherwise, we just _always_ turn on the
* write enable port on the inner memory. */
@@ -316,9 +316,7 @@ class MacroCompilerPass(mems: Option[Seq[Macro]],
}
case _ => c.modules
}
val circuit = c.copy(modules = modules)
// print(circuit.serialize)
circuit
c.copy(modules = modules)
}
}

4
tapeout/src/main/scala/transforms/macros/SynFlops.scala
View File

@@ -54,9 +54,9 @@ class SynFlopsPass(synflops: Boolean, libs: Seq[Macro]) extends firrtl.passes.Pa
WSubIndex(data, k, tpe, UNKNOWNGENDER))).reverse)
case _: UIntType => data
}
val addrReg = WRef(s"R_${i}_addr_reg", r.AddrType, RegKind)
val addrReg = WRef(s"R_${i}_addr_reg", r.addrType, RegKind)
Seq(
DefRegister(NoInfo, addrReg.name, r.AddrType, clock, zero, addrReg),
DefRegister(NoInfo, addrReg.name, r.addrType, clock, zero, addrReg),
Connect(NoInfo, memPortField(mem, s"R_$i", "clk"), clock),
Connect(NoInfo, memPortField(mem, s"R_$i", "addr"), addrReg),
Connect(NoInfo, memPortField(mem, s"R_$i", "en"), enable),

17
tapeout/src/main/scala/transforms/macros/Utils.scala
View File

@@ -17,11 +17,12 @@ case object NegativeEdge extends PortPolarity
case object PositiveEdge extends PortPolarity
object PortPolarity {
implicit def toPortPolarity(s: Any): PortPolarity =
(s: @unchecked) match {
s match {
case "active low" => ActiveLow
case "active high" => ActiveHigh
case "negative edge" => NegativeEdge
case "positive edge" => PositiveEdge
case _ => throw new firrtl.passes.PassException(s"Wrong port polarity: ${s.toString}")
}
implicit def toPortPolarity(s: Option[Any]): Option[PortPolarity] =
s map toPortPolarity
@@ -48,18 +49,18 @@ case class MacroPort(
width: BigInt,
depth: BigInt) {
val effectiveMaskGran = maskGran.getOrElse(width)
val AddrType = UIntType(IntWidth(ceilLog2(depth) max 1))
val DataType = UIntType(IntWidth(width))
val MaskType = UIntType(IntWidth(width / effectiveMaskGran))
val addrType = UIntType(IntWidth(ceilLog2(depth) max 1))
val dataType = UIntType(IntWidth(width))
val maskType = UIntType(IntWidth(width / effectiveMaskGran))
val tpe = BundleType(Seq(
Field(clockName, Flip, ClockType),
Field(addressName, Flip, AddrType)) ++
(inputName map (Field(_, Flip, DataType))) ++
(outputName map (Field(_, Default, DataType))) ++
Field(addressName, Flip, addrType)) ++
(inputName map (Field(_, Flip, dataType))) ++
(outputName map (Field(_, Default, dataType))) ++
(chipEnableName map (Field(_, Flip, BoolType))) ++
(readEnableName map (Field(_, Flip, BoolType))) ++
(writeEnableName map (Field(_, Flip, BoolType))) ++
(maskName map (Field(_, Flip, MaskType)))
(maskName map (Field(_, Flip, maskType)))
)
val ports = tpe.fields map (f => Port(
NoInfo, f.name, f.flip match { case Default => Output case Flip => Input }, f.tpe))