Fix CI tests

tapeout/src/main/scala/transforms/ResetInverter.scala

@@ -34,11 +34,12 @@ object ResetN extends Pass {
     mod.copy(ports = portsx, body = bodyx)
   }
 
-  def run(c: Circuit): Circuit =
+  def run(c: Circuit): Circuit = {
     c.copy(modules = c.modules map {
       case mod: Module if mod.name == c.main => invertReset(mod)
       case other => other
     })
+  }
 }
 
 class ResetInverterTransform extends Transform {

tapeout/src/test/scala/transforms/ResetInverterSpec.scala

@@ -22,7 +22,7 @@ class ResetNSpec extends FreeSpec with Matchers {
 
   "Inverting reset needs to be done throughout module" in {
     val optionsManager = new ExecutionOptionsManager("dsptools") with HasChiselExecutionOptions with HasFirrtlOptions {
-      firrtlOptions = firrtlOptions.copy(compilerName = "low")
+      firrtlOptions = firrtlOptions.copy(compilerName = "low", customTransforms = List(new ResetInverterTransform)),
     }
     chisel3.Driver.execute(optionsManager, () => new ExampleModuleNeedsResetInverted) match {
       case ChiselExecutionSuccess(_, chirrtl, Some(FirrtlExecutionSuccess(_, firrtl))) =>

tapeout/src/test/scala/transforms/retime/RetimeSpec.scala

@@ -27,10 +27,10 @@ class RetimeSpec extends FlatSpec with Matchers {
     val dir = uniqueDirName(gen, "RetimeModule")
     chisel3.Driver.execute(Array("-td", s"test_run_dir/$dir", "-foaf", s"test_run_dir/$dir/final"), gen) shouldBe a [ChiselExecutionSuccess]
 
-    val lines = io.Source.fromFile(s"test_run_dir/$dir/final.anno.json").getLines().map(normalized).mkString("\n")
+    val lines = io.Source.fromFile(s"test_run_dir/$dir/test_run_dir/$dir/final.anno.json").getLines().map(normalized).mkString("\n")
     lines should include("barstools.tapeout.transforms.retime.RetimeTransform")
   }
-  
+
   // TODO(azidar): need to fix/add instance annotations
   ignore should "pass simple retime instance annotation" in {
     val gen = () => new RetimeInstance()