Richard Yan
d0b274ab78
Merge branch 'main' of https://github.com/ucb-bar/chipyard into ucb-bar-main
2024-04-20 02:03:35 -07:00
Richard Yan
e75c77a08a
synthesizable radiance
2024-04-17 18:22:44 -07:00
Hansung Kim
f77f1edecc
Add fpnew packages and include dirs to vcs flags
...
This is necessary because Verilog package definitions need to be compiled before
the modules that reference them, but the compilation order is not enforced with
addResource()s.
2024-04-15 15:31:10 -07:00
Richard Yan
13766128bf
add printf script, bump gemmini and radiance
2024-04-15 10:01:47 -07:00
Jerry Zhao
4ce6198b86
Pass -top flag to VCS to avoid simulating non-tops
2024-03-19 23:49:08 -07:00
Jerry Zhao
7b3d3e54bd
Add incdirs to vcs/verilator flows
2024-03-19 23:48:51 -07:00
Vighnesh Iyer
390980e51a
bump firesim
2024-03-13 14:27:15 -07:00
Jerry Zhao
a27bc7f5ed
Bump rocket-chip to standalone diplomacy
2024-03-10 12:16:12 -07:00
Jerry Zhao
931da1d276
Bump firesim
2024-03-08 12:58:21 -08:00
Jerry Zhao
bf4d83bc39
Bump firesim
2024-02-25 16:49:30 -08:00
Hansung Kim
446e8fe245
Move vortex-specific EXTRA_SIM_PREPROC_DEFINES to mk fragment
2024-02-05 09:42:10 -08:00
Richard Yan
fd5fa7b6e1
Merge branch 'main' of https://github.com/ucb-bar/chipyard into graphics
2024-02-02 16:28:55 -08:00
joonho.whangbo
71da0c36f7
Bump fsim
2024-01-22 18:03:03 -08:00
joey0320
778e133842
Bump fsim
2024-01-20 16:50:06 -08:00
Hansung Kim
0e078b2701
Remove unnecessary make clean in run-radiance.sh
2024-01-17 11:36:40 -08:00
Hansung Kim
bf84580010
Merge remote-tracking branch 'upstream/main' into graphics
2024-01-16 22:39:37 -08:00
Hansung Kim
3190224cfe
Squelch inout coerce lint messages from vortex RTL
2024-01-16 16:32:30 -08:00
Hansung Kim
0bb2a5c6f2
Accept EXTRA_SIM_PREPROC_DEFINES in run-radiance.sh
2024-01-16 16:31:26 -08:00
Jerry Zhao
45d74f6db2
Merge remote-tracking branch 'origin/main' into symmetric_sertl
2024-01-11 11:43:24 -08:00
Jerry Zhao
d51a9a74d3
Merge remote-tracking branch 'origin/main' into clusters
2024-01-09 13:30:26 -08:00
Jerry Zhao
7c13574769
Rename cache/blocks submodules to match new chipsalliance ownership
2024-01-05 10:42:00 -08:00
Jerry Zhao
41651edbdc
Bump firesim | fix testchipip segfaults
2024-01-01 18:40:59 -08:00
Hansung Kim
fdf02063a3
Add scripts for vortex binfile setup and sim runs
2023-12-30 16:36:34 -08:00
Hansung Kim
ba6c80768e
gitignore Vortex *.bin files in sims/
2023-12-30 16:36:03 -08:00
Jerry Zhao
8600640a40
Bump verilator to v5.018
2023-12-29 19:17:01 -08:00
Jerry Zhao
1e5ebf192a
Update firesim/firechip with new testchipip packaging
2023-12-19 12:11:12 -08:00
Hansung Kim
0ea06336b5
Set preproc defines for Vortex
...
Includes GPR_RESET which uses simulation-only initial block to clear out
regfile.
2023-11-27 16:15:55 -08:00
Hansung Kim
e113d8dc3f
Add EXTRA_SIM_PREPROC_DEFINES to common-sims-flags.mk
...
This allows adding e.g. EXTRA_SIM_PREPROC_DEFINES="+define+NUM_CORES=2"
to the make command to change Vortex Verilog parameters.
2023-10-20 11:55:35 -07:00
Jerry Zhao
5145f4f243
Bump firesim
2023-10-06 17:55:49 -07:00
Jerry Zhao
eb3a0aecf4
Add PortAPI between IO and Harness blocks
2023-10-05 15:02:56 -07:00
Hansung Kim
ffe1b74e67
Add gen-collateral to Verilator include dir
...
This fixes VX_define.vh not being found when compiling Vortex verilog
sources.
2023-10-01 19:37:31 -07:00
Hansung Kim
3d7caa41e8
Merge remote-tracking branch 'upstream/main' into graphics
...
Bumped rocket-chip and testchipip to graphics
2023-10-01 17:57:36 -07:00
abejgonzalez
3c42e63732
Bump FireSim
2023-08-30 22:17:17 -07:00
abejgonzalez
44f042a152
Merge remote-tracking branch 'origin/main' into cospike-integration
2023-08-30 18:06:31 -07:00
abejgonzalez
d54007ea25
Bump FireSim
2023-08-30 17:57:23 -07:00
abejgonzalez
c7f1fe220d
Enable precommit | Format files
2023-08-28 14:56:55 -07:00
Hansung Kim
241600fea3
Merge remote-tracking branch 'upstream/main' into graphics
2023-08-23 11:51:45 -07:00
Jerry Zhao
5495d05aa0
Bump to latest rocket-chip
2023-08-22 11:28:57 -07:00
Jerry Zhao
0b097d681e
Bump firesim
2023-07-31 10:59:51 -07:00
Hansung Kim
2e3a2af0c6
run-coalperfs.sh: Fix output directory path
2023-07-22 16:28:34 -07:00
Hansung Kim
016f293da1
Add 2bit-sourceId configs to CoalescerConfigs
...
... and add those to run-coalperf.sh
It seemed before that configs with narrower sourceId are more likely to
fail because of more contention between outstanding requests, so test
more of those configs.
2023-07-22 15:41:13 -07:00
Hansung Kim
d60dacf6ea
Merge remote-tracking branch 'upstream/main' into graphics
2023-07-22 14:45:48 -07:00
Hansung Kim
d85a651324
run-coalperf.sh: disable 512-bit sbus configs
...
Currently Chipyard fails to elaborate with SBus width of 512 bits. It's
unclear if this is a problem in the coalescing unit or in Chipyard in
general. For now, only enable configs that use sbus widths up to 256
bits.
2023-07-22 14:31:57 -07:00
Hansung Kim
cbe982a7ac
run-coalperf.sh: exit on error, use output dir, don't make clean
2023-07-22 14:09:26 -07:00
Jerry Zhao
ef3409f87f
Merge remote-tracking branch 'origin/main' into rcbump
2023-07-09 23:31:16 -07:00
Jerry Zhao
610b9a25a4
Merge pull request #1484 from ucb-bar/tetheredsim
...
Provide example of tethered-config simulation with MultiHarnessBinders
2023-07-09 18:21:53 -07:00
Jerry Zhao
078bce1323
Bump to chisel3.6
2023-07-05 10:32:55 -07:00
Sagar Karandikar
65be299e17
bump firesim
2023-07-05 06:29:54 -07:00
Jerry Zhao
927d236d1f
Merge remote-tracking branch 'origin/main' into tetheredsim
2023-07-02 11:53:33 -07:00
Sagar Karandikar
73d9f292f6
bump firesim
2023-06-30 14:30:28 +00:00
