Merge branch 'main' of https://github.com/ucb-bar/chipyard into ucb-bar-main

sims/vcs/vcs.mk

@@ -54,7 +54,9 @@ VCS_NONCC_OPTS = \
 	-sverilog +systemverilogext+.sv+.svi+.svh+.svt -assert svaext +libext+.sv \
 	+v2k +verilog2001ext+.v95+.vt+.vp +libext+.v \
 	-debug_pp \
-	+incdir+$(GEN_COLLATERAL_DIR)
+	-top $(TB) \
+	+incdir+$(GEN_COLLATERAL_DIR) \
+	$(addprefix +incdir+,$(EXT_INCDIRS))
 
 VCS_PREPROC_DEFINES = \
 	+define+VCS

sims/verilator/Makefile

@@ -155,6 +155,7 @@ VERILATOR_NONCC_OPTS = \
 	-I$(GEN_COLLATERAL_DIR) \
 	--top-module $(TB) \
 	--vpi \
+	$(addprefix +incdir+,$(EXT_INCDIRS)) \
 	-f $(sim_common_files)
 
 #----------------------------------------------------------------------------------------