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Merge remote-tracking branch 'upstream/main' into graphics

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This commit is contained in:
Hansung Kim
2023-07-22 14:45:48 -07:00
parent 5c5c620afc 6dc7d6f1c3
commit d60dacf6ea
175 changed files with 5277 additions and 4019 deletions
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14
sims/common-sim-flags.mk
View File

@@ -33,3 +33,17 @@ SIM_LDFLAGS = \
-lfesvr \
-ldramsim \
$(EXTRA_SIM_LDFLAGS)
CLOCK_PERIOD ?= 1.0
RESET_DELAY ?= 777.7
SIM_PREPROC_DEFINES = \
+define+CLOCK_PERIOD=$(CLOCK_PERIOD) \
+define+RESET_DELAY=$(RESET_DELAY) \
+define+PRINTF_COND=$(TB).printf_cond \
+define+STOP_COND=!$(TB).reset \
+define+MODEL=$(MODEL) \
+define+RANDOMIZE_MEM_INIT \
+define+RANDOMIZE_REG_INIT \
+define+RANDOMIZE_GARBAGE_ASSIGN \
+define+RANDOMIZE_INVALID_ASSIGN

2
sims/firesim

Submodule sims/firesim updated: 8c85960b93...7cade06041

6
sims/vcs/Makefile
View File

@@ -25,7 +25,7 @@ sim_prefix = simv
sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)
sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug
include $(base_dir)/vcs.mk
include $(sim_dir)/vcs.mk
.PHONY: default debug
default: $(sim)
@@ -56,7 +56,7 @@ include $(base_dir)/common.mk
#########################################################################################
VCS = vcs -full64
VCS_OPTS = $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(PREPROC_DEFINES)
VCS_OPTS = $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(SIM_PREPROC_DEFINES) $(VCS_PREPROC_DEFINES)
#########################################################################################
# vcs build paths
@@ -93,7 +93,7 @@ $(output_dir)/%.fsdb: $(output_dir)/% $(sim_debug)
#########################################################################################
.PHONY: clean clean-sim clean-sim-debug
clean:
rm -rf $(gen_dir) $(sim_prefix)-* ucli.key
rm -rf $(CLASSPATH_CACHE) $(gen_dir) $(sim_prefix)-* ucli.key
clean-sim:
rm -rf $(model_dir) $(build_dir)/vc_hdrs.h $(sim) $(sim).daidir ucli.key

61
sims/vcs/vcs.mk Normal file
View File

@@ -0,0 +1,61 @@
HELP_COMPILATION_VARIABLES += \
" USE_VPD = set to '1' to build VCS simulator to emit VPD instead of FSDB."
HELP_SIMULATION_VARIABLES += \
" USE_VPD = set to '1' to run VCS simulator emitting VPD instead of FSDB."
ifndef USE_VPD
get_waveform_flag=+fsdbfile=$(1).fsdb
else
get_waveform_flag=+vcdplusfile=$(1).vpd
endif
# If ntb_random_seed unspecified, vcs uses 1 as constant seed.
# Set ntb_random_seed_automatic to actually get a random seed
ifdef RANDOM_SEED
SEED_FLAG=+ntb_random_seed=$(RANDOM_SEED)
else
SEED_FLAG=+ntb_random_seed_automatic
endif
CLOCK_PERIOD ?= 1.0
RESET_DELAY ?= 777.7
#----------------------------------------------------------------------------------------
# gcc configuration/optimization
#----------------------------------------------------------------------------------------
include $(base_dir)/sims/common-sim-flags.mk
VCS_CXXFLAGS = $(SIM_CXXFLAGS)
VCS_LDFLAGS = $(SIM_LDFLAGS)
# vcs requires LDFLAGS to not include library names (i.e. -l needs to be separate)
VCS_CC_OPTS = \
-CFLAGS "$(VCS_CXXFLAGS)" \
-LDFLAGS "$(filter-out -l%,$(VCS_LDFLAGS))" \
$(filter -l%,$(VCS_LDFLAGS))
VCS_NONCC_OPTS = \
-notice \
-line \
+lint=all,noVCDE,noONGS,noUI \
-error=PCWM-L \
-error=noZMMCM \
-timescale=1ns/10ps \
-quiet \
-q \
+rad \
+vcs+lic+wait \
+vc+list \
-f $(sim_common_files) \
-sverilog +systemverilogext+.sv+.svi+.svh+.svt -assert svaext +libext+.sv \
+v2k +verilog2001ext+.v95+.vt+.vp +libext+.v \
-debug_pp \
+incdir+$(GEN_COLLATERAL_DIR)
VCS_PREPROC_DEFINES = \
+define+VCS
ifndef USE_VPD
VCS_PREPROC_DEFINES += +define+FSDB
endif

68
sims/verilator/Makefile
View File

@@ -28,13 +28,11 @@ sim_prefix = simulator
sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)
sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug
WAVEFORM_FLAG=-v$(sim_out_name).vcd
include $(base_dir)/sims/common-sim-flags.mk
# If verilator seed unspecified, verilator uses srand as random seed
ifdef RANDOM_SEED
SEED_FLAG=+verilator+seed+I$(RANDOM_SEED)
SEED_FLAG=+verilator+seed+$(RANDOM_SEED)
else
SEED_FLAG=
endif
@@ -47,23 +45,7 @@ debug: $(sim_debug)
# simulaton requirements
#########################################################################################
SIM_FILE_REQS += \
$(CHIPYARD_RSRCS_DIR)/csrc/emulator.cc \
$(ROCKETCHIP_RSRCS_DIR)/csrc/verilator.h \
# the following files are needed for emulator.cc to compile (even if they aren't part of the RTL build)
SIM_FILE_REQS += \
$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimSerial.cc \
$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_tsi.cc \
$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_tsi.h \
$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimDRAM.cc \
$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm.h \
$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm.cc \
$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm_dramsim2.h \
$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm_dramsim2.cc \
$(ROCKETCHIP_RSRCS_DIR)/csrc/SimDTM.cc \
$(ROCKETCHIP_RSRCS_DIR)/csrc/SimJTAG.cc \
$(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.h \
$(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.cc
$(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v
# copy files and add -FI for *.h files in *.f
$(sim_files): $(SIM_FILE_REQS) $(ALL_MODS_FILELIST) | $(GEN_COLLATERAL_DIR)
@@ -87,12 +69,15 @@ HELP_COMPILATION_VARIABLES += \
" 'all' if full verilator runtime profiling" \
" 'threads' if runtime thread profiling only" \
" VERILATOR_THREADS = how many threads the simulator will use (default 1)" \
" VERILATOR_FST_MODE = enable FST waveform instead of VCD. use with debug build"
" USE_FST = set to '1' to build Verilator simulator to emit FST instead of VCD."
HELP_SIMULATION_VARIABLES += \
" USE_FST = set to '1' to run Verilator simulator emitting FST instead of VCD."
#########################################################################################
# verilator/cxx binary and flags
#########################################################################################
VERILATOR := verilator --cc --exe
VERILATOR := verilator --main --timing --cc --exe
#----------------------------------------------------------------------------------------
# user configs
@@ -107,10 +92,11 @@ RUNTIME_PROFILING_VFLAGS := $(if $(filter $(VERILATOR_PROFILE),all),\
VERILATOR_THREADS ?= 1
RUNTIME_THREADS := --threads $(VERILATOR_THREADS) --threads-dpi all
VERILATOR_FST_MODE ?= 0
TRACING_OPTS := $(if $(filter $(VERILATOR_FST_MODE),0),\
USE_FST ?= 0
TRACING_OPTS := $(if $(filter $(USE_FST),0),\
--trace,--trace-fst --trace-threads 1)
TRACING_CFLAGS := $(if $(filter $(VERILATOR_FST_MODE),0),,-DCY_FST_TRACE)
# TODO: consider renaming +vcdfile in TestDriver.v to +waveformfile (or similar)
get_waveform_flag = +vcdfile=$(1).$(if $(filter $(USE_FST),0),vcd,fst)
#----------------------------------------------------------------------------------------
# verilation configuration/optimization
@@ -153,9 +139,8 @@ TIMESCALE_OPTS := $(shell verilator --version | perl -lne 'if (/(\d.\d+)/ && $$1
# see: https://github.com/ucb-bar/riscv-mini/issues/31
MAX_WIDTH_OPTS = $(shell verilator --version | perl -lne 'if (/(\d.\d+)/ && $$1 > 4.016) { print "--max-num-width 1048576"; }')
PREPROC_DEFINES := \
+define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \
+define+STOP_COND=\$$c\(\"done_reset\"\)
VERILATOR_PREPROC_DEFINES = \
+define+VERILATOR
VERILATOR_NONCC_OPTS = \
$(RUNTIME_PROFILING_VFLAGS) \
@@ -165,8 +150,9 @@ VERILATOR_NONCC_OPTS = \
-Wno-fatal \
$(TIMESCALE_OPTS) \
$(MAX_WIDTH_OPTS) \
$(PREPROC_DEFINES) \
--top-module $(VLOG_MODEL) \
$(SIM_PREPROC_DEFINES) \
$(VERILATOR_PREPROC_DEFINES) \
--top-module $(TB) \
--vpi \
-f $(sim_common_files)
@@ -176,12 +162,8 @@ VERILATOR_NONCC_OPTS = \
VERILATOR_CXXFLAGS = \
$(SIM_CXXFLAGS) \
$(RUNTIME_PROFILING_CFLAGS) \
$(TRACING_CFLAGS) \
-D__STDC_FORMAT_MACROS \
-DTEST_HARNESS=V$(VLOG_MODEL) \
-DVERILATOR \
-include $(build_dir)/$(long_name).plusArgs \
-include $(GEN_COLLATERAL_DIR)/verilator.h
-include $(build_dir)/$(long_name).plusArgs
VERILATOR_LDFLAGS = $(SIM_LDFLAGS)
@@ -200,11 +182,11 @@ VERILATOR_OPTS = $(VERILATOR_CC_OPTS) $(VERILATOR_NONCC_OPTS)
model_dir = $(build_dir)/$(long_name)
model_dir_debug = $(build_dir)/$(long_name).debug
model_header = $(model_dir)/V$(VLOG_MODEL).h
model_header_debug = $(model_dir_debug)/V$(VLOG_MODEL).h
model_header = $(model_dir)/V$(TB).h
model_header_debug = $(model_dir_debug)/V$(TB).h
model_mk = $(model_dir)/V$(VLOG_MODEL).mk
model_mk_debug = $(model_dir_debug)/V$(VLOG_MODEL).mk
model_mk = $(model_dir)/V$(TB).mk
model_mk_debug = $(model_dir_debug)/V$(TB).mk
#########################################################################################
# build makefile fragment that builds the verilator sim rules
@@ -218,17 +200,17 @@ $(model_mk): $(sim_common_files) $(EXTRA_SIM_REQS)
$(model_mk_debug): $(sim_common_files) $(EXTRA_SIM_REQS)
rm -rf $(model_dir_debug)
mkdir -p $(model_dir_debug)
$(VERILATOR) $(VERILATOR_OPTS) $(EXTRA_SIM_SOURCES) -o $(sim_debug) $(TRACING_OPTS) -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)"
$(VERILATOR) $(VERILATOR_OPTS) +define+DEBUG $(EXTRA_SIM_SOURCES) -o $(sim_debug) $(TRACING_OPTS) -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)"
touch $@
#########################################################################################
# invoke make to make verilator sim rules
#########################################################################################
$(sim): $(model_mk) $(dramsim_lib)
$(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir) -f V$(VLOG_MODEL).mk
$(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir) -f V$(TB).mk
$(sim_debug): $(model_mk_debug) $(dramsim_lib)
$(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir_debug) -f V$(VLOG_MODEL).mk
$(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir_debug) -f V$(TB).mk
#########################################################################################
# create a verilator vpd rule
@@ -244,7 +226,7 @@ $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
#########################################################################################
.PHONY: clean clean-sim clean-sim-debug
clean:
rm -rf $(gen_dir) $(sim_prefix)-*
rm -rf $(CLASSPATH_CACHE) $(gen_dir) $(sim_prefix)-*
clean-sim:
rm -rf $(model_dir) $(sim)

49
sims/xcelium/Makefile
View File

@@ -39,7 +39,7 @@ sim_workdir = $(build_dir)/xcelium.d
sim_run_tcl = $(build_dir)/xcelium_run.tcl
sim_debug_run_tcl = $(build_dir)/xcelium_debug_run.tcl
include $(base_dir)/xcelium.mk
include $(base_dir)/sims/xcelium/xcelium.mk
.PHONY: default debug
default: $(sim)
@@ -77,7 +77,6 @@ XCELIUM_OPTS = $(XCELIUM_CC_OPTS) $(XCELIUM_NONCC_OPTS) $(PREPROC_DEFINES)
model_dir = $(build_dir)/$(long_name)
model_dir_debug = $(build_dir)/$(long_name).debug
#########################################################################################
# xcelium simulator rules
#########################################################################################
@@ -87,37 +86,35 @@ $(sim_workdir): $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS)
$(XCELIUM) -elaborate $(XCELIUM_OPTS) $(EXTRA_SIM_SOURCES) $(XCELIUM_COMMON_ARGS)
$(sim_run_tcl): $(sim_workdir)
echo "$$CAD_INFO_HEADER" > $(sim_run_tcl)
echo "run" >> $(sim_run_tcl)
echo "exit" >> $(sim_run_tcl)
echo "$$CAD_INFO_HEADER" > $@
echo "run" >> $@
echo "exit" >> $@
# The system libstdc++ may not link correctly with some of our dynamic libs, so
# force loading the conda one (if present) with LD_PRELOAD
$(sim): $(sim_workdir) $(sim_run_tcl)
echo "#!/usr/bin/env bash" > $(sim)
echo "$$CAD_INFO_HEADER" >> $(sim)
cat arg-reshuffle >> $(sim)
echo "LD_PRELOAD=$(base_dir)/.conda-env/lib/libstdc++.so.6 $(XCELIUM) +permissive -R -input $(sim_run_tcl) $(XCELIUM_COMMON_ARGS) +permissive-off \$$INPUT_ARGS" >> $(sim)
chmod +x $(sim)
echo "#!/usr/bin/env bash" > $@
echo "$$CAD_INFO_HEADER" >> $@
cat arg-reshuffle >> $@
echo "LD_PRELOAD=$(CONDA_PREFIX)/lib/libstdc++.so.6 $(XCELIUM) +permissive -R -input $(sim_run_tcl) $(XCELIUM_COMMON_ARGS) +permissive-off \$$INPUT_ARGS" >> $@
chmod +x $@
$(sim_debug_run_tcl): $(sim_workdir)
echo "$$CAD_INFO_HEADER" > $(sim_debug_run_tcl)
echo "database -open default_vcd_dump -vcd -into \$$env(XCELIUM_WAVEFORM_FLAG)" >> $(sim_debug_run_tcl)
echo "set probe_packed_limit 64k" >> $(sim_debug_run_tcl)
echo "probe -create $(TB) -database default_vcd_dump -depth all -all" >> $(sim_debug_run_tcl)
echo "run" >> $(sim_debug_run_tcl)
echo "database -close default_vcd_dump" >> $(sim_debug_run_tcl)
echo "exit" >> $(sim_debug_run_tcl)
echo "$$CAD_INFO_HEADER" > $@
echo "database -open default_vcd_dump -vcd -into \$$env(XCELIUM_WAVEFORM_FLAG)" >> $@
echo "set probe_packed_limit 64k" >> $@
echo "probe -create $(TB) -database default_vcd_dump -depth all -all" >> $@
echo "run" >> $@
echo "database -close default_vcd_dump" >> $@
echo "exit" >> $@
$(sim_debug): $(sim_workdir) $(sim_debug_run_tcl)
echo "#!/usr/bin/env bash" > $(sim_debug)
echo "$$CAD_INFO_HEADER" >> $(sim_debug)
cat arg-reshuffle >> $(sim_debug)
echo "export XCELIUM_WAVEFORM_FLAG=\$$XCELIUM_WAVEFORM_FLAG" >> $(sim_debug)
echo "LD_PRELOAD=$(base_dir)/.conda-env/lib/libstdc++.so.6 $(XCELIUM) +permissive -R -input $(sim_debug_run_tcl) $(XCELIUM_COMMON_ARGS) +permissive-off \$$INPUT_ARGS" >> $(sim_debug)
chmod +x $(sim_debug)
echo "#!/usr/bin/env bash" > $@
echo "$$CAD_INFO_HEADER" >> $@
cat arg-reshuffle >> $@
echo "export XCELIUM_WAVEFORM_FLAG=\$$XCELIUM_WAVEFORM_FLAG" >> $@
echo "LD_PRELOAD=$(CONDA_PREFIX)/lib/libstdc++.so.6 $(XCELIUM) +permissive -R -input $(sim_debug_run_tcl) $(XCELIUM_COMMON_ARGS) +permissive-off \$$INPUT_ARGS" >> $@
chmod +x $@
#########################################################################################
# create vcd rules
@@ -131,7 +128,7 @@ $(output_dir)/%.vcd: $(output_dir)/% $(sim_debug)
#########################################################################################
.PHONY: clean clean-sim clean-sim-debug
clean:
rm -rf $(gen_dir) $(sim_prefix)-*
rm -rf $(CLASSPATH_CACHE) $(gen_dir) $(sim_prefix)-*
clean-sim:
rm -rf $(model_dir) $(sim) $(sim_workdir) $(sim_run_tcl) ucli.key bpad_*.err sigusrdump.out dramsim*.log

65
sims/xcelium/xcelium.mk Normal file
View File

@@ -0,0 +1,65 @@
get_waveform_flag=+vcdfile=$(1).vcd
# If ntb_random_seed unspecified, xcelium uses 1 as constant seed.
# Set ntb_random_seed_automatic to actually get a random seed
ifdef RANDOM_SEED
SEED_FLAG=+ntb_random_seed=$(RANDOM_SEED)
else
SEED_FLAG=+ntb_random_seed_automatic
endif
CLOCK_PERIOD ?= 1.0
RESET_DELAY ?= 777.7
#----------------------------------------------------------------------------------------
# gcc configuration/optimization
#----------------------------------------------------------------------------------------
include $(base_dir)/sims/common-sim-flags.mk
XC_CXX_PREFIX=-Wcxx,
XC_LD_PREFIX=-Wld,
REMOVE_RPATH=-Wl,-rpath%
XCELIUM_CXXFLAGS = $(addprefix $(XC_CXX_PREFIX), $(SIM_CXXFLAGS))
XCELIUM_LDFLAGS = $(addprefix $(XC_LD_PREFIX), $(filter-out $(REMOVE_RPATH), $(SIM_LDFLAGS)))
XCELIUM_COMMON_ARGS = \
-64bit \
-xmlibdirname $(sim_workdir) \
-l /dev/null \
-log_xmsc_run /dev/null
XCELIUM_CC_OPTS = \
$(XCELIUM_CXXFLAGS) \
$(XCELIUM_LDFLAGS) \
-enable_rpath
XCELIUM_NONCC_OPTS = \
-fast_recompilation \
-top $(TB) \
-sv \
-ALLOWREDEFINITION \
-timescale 1ns/10ps \
-define INTCNOPWR \
-define INTC_NO_PWR_PINS \
-define INTC_EMULATION \
-f $(sim_common_files) \
-glsperf \
-notimingchecks \
-delay_mode zero
PREPROC_DEFINES = \
-define XCELIUM \
-define CLOCK_PERIOD=$(CLOCK_PERIOD) \
-define RESET_DELAY=$(RESET_DELAY) \
-define PRINTF_COND=$(TB).printf_cond \
-define STOP_COND=!$(TB).reset \
-define MODEL=$(MODEL) \
-define RANDOMIZE_MEM_INIT \
-define RANDOMIZE_REG_INIT \
-define RANDOMIZE_GARBAGE_ASSIGN \
-define RANDOMIZE_INVALID_ASSIGN