Add incdirs to vcs/verilator flows

2024-03-19 23:48:51 -07:00
parent edf6d9ed19
commit 7b3d3e54bd
2 changed files with 3 additions and 1 deletions
--- a/sims/vcs/vcs.mk
+++ b/sims/vcs/vcs.mk
@@ -51,7 +51,8 @@ VCS_NONCC_OPTS = \
 	-sverilog +systemverilogext+.sv+.svi+.svh+.svt -assert svaext +libext+.sv \
 	+v2k +verilog2001ext+.v95+.vt+.vp +libext+.v \
 	-debug_pp \
-	+incdir+$(GEN_COLLATERAL_DIR)
+	+incdir+$(GEN_COLLATERAL_DIR) \
+	$(addprefix +incdir+,$(EXT_INCDIRS))

 VCS_PREPROC_DEFINES = \
 	+define+VCS
--- a/sims/verilator/Makefile
+++ b/sims/verilator/Makefile
@@ -154,6 +154,7 @@ VERILATOR_NONCC_OPTS = \
 	$(VERILATOR_PREPROC_DEFINES) \
 	--top-module $(TB) \
 	--vpi \
+	$(addprefix +incdir+,$(EXT_INCDIRS)) \
 	-f $(sim_common_files)

 #----------------------------------------------------------------------------------------