Jerry Zhao
|
45d74f6db2
|
Merge remote-tracking branch 'origin/main' into symmetric_sertl
|
2024-01-11 11:43:24 -08:00 |
|
Jerry Zhao
|
d51a9a74d3
|
Merge remote-tracking branch 'origin/main' into clusters
|
2024-01-09 13:30:26 -08:00 |
|
Jerry Zhao
|
96ffc8f0a1
|
git push origin symmetric_sertl
Merge remote-tracking branch 'origin/main' into symmetric_sertl
|
2024-01-01 19:14:21 -08:00 |
|
Jerry Zhao
|
0fa09da5c1
|
Remove MBus spad from configs that do not support it
|
2023-12-30 07:03:34 -08:00 |
|
Jerry Zhao
|
835562238a
|
Explicitly pass chipId to all HarnessBinders
|
2023-12-26 18:37:39 -08:00 |
|
Jerry Zhao
|
604cb6358f
|
Bump fpga-platforms to new organized testchipip
|
2023-12-19 12:33:37 -08:00 |
|
Jerry Zhao
|
b02621db35
|
Merge remote-tracking branch 'origin/main' into clusters
|
2023-12-16 17:00:34 -08:00 |
|
Jerry Zhao
|
e7f10348b0
|
Merge remote-tracking branch 'origin/main' into clusters
|
2023-12-15 16:46:51 -08:00 |
|
Jerry Zhao
|
30ac9dc2c8
|
Merge remote-tracking branch 'origin/main' into tcip-bump
|
2023-12-14 10:58:57 -08:00 |
|
-T.K.-
|
e078fcba49
|
REFACTOR: rename arty35t explicitly
|
2023-12-04 01:54:59 -08:00 |
|
Jerry Zhao
|
a8766ea8fc
|
Precisely specify bus frequencies
|
2023-10-31 14:25:16 -07:00 |
|
Jerry Zhao
|
3fa3d745b9
|
Support breaking out ChipTop I/O out of the expected bundle type
|
2023-10-30 21:25:11 -07:00 |
|
Jerry Zhao
|
a5597fd32f
|
Support using HarnessBinders without IOBinders
|
2023-10-25 11:49:16 -07:00 |
|
Jerry Zhao
|
1e26618e8d
|
Fix fpga platforms cbus freq
|
2023-10-21 15:48:01 -07:00 |
|
Jerry Zhao
|
eb3a0aecf4
|
Add PortAPI between IO and Harness blocks
|
2023-10-05 15:02:56 -07:00 |
|
Jerry Zhao
|
5495d05aa0
|
Bump to latest rocket-chip
|
2023-08-22 11:28:57 -07:00 |
|
Jerry Zhao
|
2077e4304d
|
Explicitly provide refClockFreqMHz to harnessClockInstantiator
|
2023-05-13 11:18:03 -07:00 |
|
Jerry Zhao
|
b8e95e0305
|
Rename implicit clock/reset to referenceclock/reset
|
2023-05-12 15:11:44 -07:00 |
|
Jerry Zhao
|
607c2b5a73
|
Unify multi-node btw chipyard/firechip | unify harness clocking
|
2023-05-12 08:41:34 -07:00 |
|
Jerry Zhao
|
64ad77bbcf
|
Make FPGA flows use the harnessClockInstantiator
|
2023-05-11 15:04:04 -07:00 |
|
Jerry Zhao
|
ac281daa78
|
Move TestHarness to chipyard.harness, make chipyard/harness directory
|
2023-05-08 08:00:56 -07:00 |
|
Jerry Zhao
|
e93bc3bed7
|
Fix Arty FPGA reset harness binder
|
2023-04-01 13:53:56 -07:00 |
|
Jerry Zhao
|
6abf970ccb
|
Fix ArtyJTAG matching
|
2023-04-01 10:23:22 -07:00 |
|
Jerry Zhao
|
df2e5ad9dc
|
Bump to latest rocket-chip/chisel3.5.6
|
2023-03-28 16:48:27 -07:00 |
|
Jerry Zhao
|
85fa9d1120
|
Add ARTY100t bringup + TSI-over-UART
|
2023-02-14 15:01:52 -08:00 |
|
abejgonzalez
|
292cc753ce
|
Run pre-commit on all files
|
2022-12-21 15:59:46 -08:00 |
|
Abraham Gonzalez
|
8e851b0285
|
Merge pull request #1278 from Lorilandly/vc707fpga
Add support for VC707 FPGA board changelog:added
|
2022-12-14 19:16:49 -08:00 |
|
-T.K.-
|
1b7457d2fc
|
FIX: fix Arty FPGA reset signal (#1257)
|
2022-12-07 19:34:35 -08:00 |
|
Lori Li
|
0724431873
|
Clean up code
|
2022-11-30 16:56:09 +09:00 |
|
James Dunn
|
8e59db02fd
|
Merge pull request #968 from duyhieubui/master
Fixes UART portmap for Arty.
|
2021-10-13 13:25:10 -07:00 |
|
Jerry Zhao
|
f668ffdb03
|
Switch PRCI to HarnessBinder/IOBinders
|
2021-09-29 11:39:52 -07:00 |
|
Duy-Hieu Bui
|
d9858c1dc8
|
Fixes UART portmap for Arty.
|
2021-09-03 05:02:36 +07:00 |
|
Jerry Zhao
|
ed2bfa8249
|
Don't pass JTAG oe signal off-chip (#832)
|
2021-03-24 01:08:46 -07:00 |
|
abejgonzalez
|
09ef82cabf
|
Update harnessClk/Rst naming to buildtop | Small docs cleanup
|
2021-03-22 13:11:12 -07:00 |
|
abejgonzalez
|
b797077334
|
Fix Arty documentation link
|
2020-12-27 22:00:06 -08:00 |
|
abejgonzalez
|
8f6de22e72
|
Fixed TinyRocketConfig | Small cleanup to VCU118/Arty configs
|
2020-11-23 16:30:39 -08:00 |
|
abejgonzalez
|
661a7701a7
|
Share DigitalTop/ChipyardSystem | Fix small naming compile error
|
2020-11-23 15:46:03 -08:00 |
|
James Dunn
|
95e8365105
|
Small change to Arty reset binder name, per Jerry's PR comment.
|
2020-11-18 16:53:37 -08:00 |
|
Abraham Gonzalez
|
5a4cad0172
|
Merge pull request #6 from ucb-bar/local-fpga-support-docs
Local fpga support docs
|
2020-11-06 21:03:15 -08:00 |
|
James Dunn
|
98fcea7b57
|
Adding initial Arty documentation; will be expanded further.
|
2020-11-06 17:25:05 -08:00 |
|
abejgonzalez
|
c721d897f3
|
Point to SiFive license | Add require on Arty
|
2020-11-06 10:18:10 -08:00 |
|
abejgonzalez
|
b0fc0457aa
|
Use Chipyard configs as base (Arty)
|
2020-11-05 20:46:03 -08:00 |
|
abejgonzalez
|
a281869041
|
Fix Arty merge and errors from CY bump
|
2020-11-05 15:04:44 -08:00 |
|
abejgonzalez
|
a7ab0dab59
|
Updated VCU118 | Bumped naming on Arty
|
2020-11-05 13:59:10 -08:00 |
|
abejgonzalez
|
3994bcecdf
|
Merge remote-tracking branch 'secret/local-fpga-arty-harnessbinders' into local-fpga-support
|
2020-11-05 11:08:36 -08:00 |
|
abejgonzalez
|
dda7622c29
|
temp commit
|
2020-10-14 14:49:22 -07:00 |
|
James Dunn
|
895dcd6831
|
referencing fully qualified chipyard.harness.OverrideHarnessBinder to debug import issue.
|
2020-10-11 11:12:33 -07:00 |
|
James Dunn
|
dca56cd858
|
Removing redefinitions of HasHarnessSignalReferences and HasTestHarnessFunctions in TestHarness.scala.
|
2020-10-10 19:55:02 -07:00 |
|
James Dunn
|
54acfe71fc
|
Some HarnessBinder testing with Jerry's debug suggestions.
|
2020-10-10 13:45:27 -07:00 |
|
dunn
|
7d1a1539e6
|
Initial pass at HarnessBinders for Arty.
|
2020-10-09 23:17:36 -07:00 |
|