dunn
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252f9c6a12
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Beginning to modify Arty TestHarness to conform with HarnessBinders. Currently does not compile; debugging.
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2020-10-07 11:55:16 -07:00 |
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James Dunn
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afc085a5f4
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Removed AON block from E300 design. Debug over JTAG still functioning.
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2020-10-04 18:13:47 -07:00 |
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James Dunn
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9135cda959
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Bypassing AON for system.reset. Using reset_core in ArtyShell test harness, which is derived from Xilinx reset IP block's mb_reset. Changing dutReset to same reset_core.
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2020-09-17 13:43:28 -07:00 |
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abejgonzalez
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2580073d75
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Comment cleanup
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2020-09-07 15:30:21 -07:00 |
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abejgonzalez
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c49eef3224
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Small cleanup to CY DigitalTop | Move E300 configs to unique folder
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2020-09-07 15:26:30 -07:00 |
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abejgonzalez
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a8083aa570
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First pass at fpga-shells with IOBinders
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2020-09-07 11:48:27 -07:00 |
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abejgonzalez
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8eb807a2fd
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Use DigitalTop in Platform | Use Chipyard BootRom
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2020-09-04 18:56:32 -07:00 |
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abejgonzalez
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0656c5da4f
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First pass on using CY make system
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2020-09-03 20:29:19 -07:00 |
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James Dunn
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a8834c7766
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First draft of local FPGA support, targeting ARTY. Able to build verilog and bitfile for Rocket + Chipyard GCD example. To test, add GCD mixin to fpga/src/main/scala/arty/Config.scala, run make -f Makefile.e300artydevkit verilog and make -f Makefile.e300artydevkit mcs in fpga directory. Output will be in fpga/build.
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2020-09-02 12:48:44 -07:00 |
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