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Fixed TinyRocketConfig | Small cleanup to VCU118/Arty configs

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This commit is contained in:
abejgonzalez
2020-11-23 16:30:39 -08:00
parent 661a7701a7
commit 8f6de22e72
4 changed files with 14 additions and 7 deletions
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5
fpga/src/main/scala/arty/Configs.scala
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@@ -33,10 +33,7 @@ class WithArtyTweaks extends Config(
new WithArtyResetHarnessBinder ++
new WithDebugResetPassthrough ++
new WithDefaultPeripherals ++
new freechips.rocketchip.subsystem.WithNBanks(0) ++ // remove L2$
new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove backing memory
new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++
new freechips.rocketchip.subsystem.WithIncoherentBusTopology)
new freechips.rocketchip.subsystem.WithNBreakpoints(2))
class TinyRocketArtyConfig extends Config(
new WithArtyTweaks ++

4
fpga/src/main/scala/vcu118/Configs.scala
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@@ -26,7 +26,6 @@ class WithDefaultPeripherals extends Config((site, here, up) => {
})
class WithSystemModifications extends Config((site, here, up) => {
case DebugModuleKey => None // disable debug module
case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = Some(site(FPGAFrequencyKey).toInt*1000000))
case DTSTimebase => BigInt(1000000)
case BootROMLocated(x) => up(BootROMLocated(x), site).map { p =>
@@ -55,7 +54,8 @@ class WithVCU118Tweaks extends Config(
new WithTLIOPassthrough ++
new WithDefaultPeripherals ++
new WithTLBackingMemory ++ // use TL backing memory
new WithSystemModifications ++ // remove debug module, setup busses, use sdboot bootrom, setup ext. mem. size, use new dig. top
new WithSystemModifications ++ // setup busses, use sdboot bootrom, setup ext. mem. size
new chipyard.config.WithNoDebug ++ // remove debug module
new freechips.rocketchip.subsystem.WithoutTLMonitors ++
new freechips.rocketchip.subsystem.WithNMemoryChannels(1))

4
generators/chipyard/src/main/scala/ConfigFragments.scala
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@@ -177,6 +177,10 @@ class WithNoDebug extends Config((site, here, up) => {
case DebugModuleKey => None
})
class WithTLSerialLocation(masterWhere: TLBusWrapperLocation, slaveWhere: TLBusWrapperLocation) extends Config((site, here, up) => {
case SerialTLAttachKey => up(SerialTLAttachKey, site).copy(masterWhere = masterWhere, slaveWhere = slaveWhere)
})
class WithTileFrequency(fMHz: Double) extends ClockNameContainsAssignment("core", fMHz)
class WithPeripheryBusFrequencyAsDefault extends Config((site, here, up) => {

8
generators/chipyard/src/main/scala/config/RocketConfigs.scala
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@@ -11,7 +11,13 @@ class RocketConfig extends Config(
new chipyard.config.AbstractConfig)
class TinyRocketConfig extends Config(
new freechips.rocketchip.subsystem.With1TinyCore ++ // single tiny rocket-core
new chipyard.config.WithTLSerialLocation(
freechips.rocketchip.subsystem.FBUS,
freechips.rocketchip.subsystem.PBUS) ++ // attach TL serial adapter to f/p busses
new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++ // use incoherent bus topology
new freechips.rocketchip.subsystem.WithNBanks(0) ++ // remove L2$
new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove backing memory
new freechips.rocketchip.subsystem.With1TinyCore ++ // single tiny rocket-core
new chipyard.config.AbstractConfig)
class HwachaRocketConfig extends Config(