Merge remote-tracking branch 'origin/main' into clusters

2023-12-15 15:53:35 -08:00
parent c5921ddef2 f882280290
commit e7f10348b0
80 changed files with 3722 additions and 2870 deletions
--- a/.github/actions/create-conda-env/action.yml
+++ b/.github/actions/create-conda-env/action.yml
@@ -14,12 +14,25 @@ runs:
          conda-lock install --conda $(which conda) -n ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-esp-tools ./conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml
          conda deactivate

-          echo "Add extra toolchain collateral to RISC-V install area"
+          echo "Add extra toolchain collateral + CIRCT to RISC-V install area"
+          git submodule update --init ./tools/install-circt
          conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-riscv-tools
          ./scripts/build-toolchain-extra.sh riscv-tools -p $CONDA_PREFIX/riscv-tools
+          ./tools/install-circt/bin/download-release-or-nightly-circt.sh \
+              -f circt-full-shared-linux-x64.tar.gz \
+              -i $CONDA_PREFIX \
+              -v version-file \
+              -x ./conda-reqs/circt.json \
+              -g ${{ github.token }}
          conda deactivate
          conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-esp-tools
          ./scripts/build-toolchain-extra.sh esp-tools -p $CONDA_PREFIX/esp-tools
+          ./tools/install-circt/bin/download-release-or-nightly-circt.sh \
+              -f circt-full-shared-linux-x64.tar.gz \
+              -i $CONDA_PREFIX \
+              -v version-file \
+              -x ./conda-reqs/circt.json \
+              -g ${{ github.token }}
          conda deactivate
        fi
      shell: bash -leo pipefail {0}
--- a/.github/scripts/check-commit.sh
+++ b/.github/scripts/check-commit.sh
@@ -45,7 +45,7 @@ search () {
    done
 }

-submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle")
+submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils")
 dir="generators"
 branches=("master" "main" "dev")
 search
@@ -81,14 +81,20 @@ dir="toolchains"
 branches=("master")
 search

+submodules=("firesim")
+dir="sims"
+branches=("main")
+search
+
+
 submodules=("coremark" "firemarshal" "nvdla-workload" "spec2017")
 dir="software"
 branches=("master" "dev")
 search

-submodules=("DRAMSim2" "axe" "barstools" "dsptools" "rocket-dsp-utils" "torture")
+submodules=("DRAMSim2" "axe" "barstools" "dsptools" "rocket-dsp-utils" "torture" "fixedpoint" "cde")
 dir="tools"
-branches=("master" "dev")
+branches=("master" "dev" "main")
 search

 submodules=("fpga-shells")
--- a/.github/scripts/defaults.sh
+++ b/.github/scripts/defaults.sh
@@ -30,11 +30,11 @@ REMOTE_COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache
 declare -A grouping
 grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone chipyard-prefetchers chipyard-shuttle"
 grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboom chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike chipyard-tethered"
-grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla"
+grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla chipyard-aes256ecb"
 grouping["group-constellation"]="chipyard-constellation"
 grouping["group-tracegen"]="tracegen tracegen-boom"
 grouping["group-other"]="icenet testchipip constellation rocketchip-amba rocketchip-tlsimple rocketchip-tlwidth rocketchip-tlxbar chipyard-clusters"
-grouping["group-fpga"]="arty arty100t nexysvideo vc707 vcu118"
+grouping["group-fpga"]="arty35t arty100t nexysvideo vc707 vcu118"

 # key value store to get the build strings
 declare -A mapping
@@ -68,6 +68,7 @@ mapping["chipyard-multiclock-rocket"]=" CONFIG=MulticlockRocketConfig"
 mapping["chipyard-nomem-scratchpad"]=" CONFIG=MMIOScratchpadOnlyRocketConfig"
 mapping["chipyard-constellation"]=" CONFIG=SharedNoCConfig"
 mapping["chipyard-clusters"]=" CONFIG=ClusteredRocketConfig verilog"
+mapping["chipyard-aes256ecb"]=" CONFIG=AES256ECBRocketConfig"

 mapping["constellation"]=" SUB_PROJECT=constellation"
 mapping["firesim"]="SCALA_TEST=firesim.firesim.RocketNICF1Tests"
@@ -79,7 +80,7 @@ mapping["rocketchip-tlsimple"]="SUB_PROJECT=rocketchip CONFIG=TLSimpleUnitTestCo
 mapping["rocketchip-tlwidth"]="SUB_PROJECT=rocketchip CONFIG=TLWidthUnitTestConfig"
 mapping["rocketchip-tlxbar"]="SUB_PROJECT=rocketchip CONFIG=TLXbarUnitTestConfig"

-mapping["arty"]="SUB_PROJECT=arty verilog"
+mapping["arty35t"]="SUB_PROJECT=arty35t verilog"
 mapping["arty100t"]="SUB_PROJECT=arty100t verilog"
 mapping["nexysvideo"]="SUB_PROJECT=nexysvideo verilog"
 mapping["vc707"]="SUB_PROJECT=vc707 verilog"
--- a/.github/workflows/chipyard-full-flow.yml
+++ b/.github/workflows/chipyard-full-flow.yml
@@ -65,7 +65,7 @@ jobs:
    name: setup-repo
    needs: [change-filters, cancel-prior-workflows]
    if: needs.change-filters.outputs.needs-rtl == 'true'
-    runs-on: jktqos
+    runs-on: as4
    steps:
      - name: Delete old checkout
        run: |
@@ -88,7 +88,7 @@ jobs:
  run-cfg-finder:
    name: run-cfg-finder
    needs: [setup-repo]
-    runs-on: jktqos
+    runs-on: as4
    steps:
      - name: Run config finder
        run: |
@@ -101,7 +101,7 @@ jobs:
  run-tutorial:
    name: run-tutorial
    needs: [setup-repo]
-    runs-on: jktqos
+    runs-on: as4
    steps:
      - name: Run smoke test
        run: |
@@ -124,7 +124,7 @@ jobs:
          conda config --add channels litex-hub

          # installs for example-sky130.yml
-          conda create -y --prefix ./.conda-sky130 open_pdks.sky130a=1.0.399_0_g63dbde9
+          conda create -y --prefix ./.conda-sky130 open_pdks.sky130a=1.0.457_0_g32e8f23
          git clone https://github.com/rahulk29/sram22_sky130_macros.git

          # installs for example-openroad.yml
@@ -170,7 +170,7 @@ jobs:
  cleanup:
    name: cleanup
    needs: [run-tutorial]
-    runs-on: jktqos
+    runs-on: as4
    if: ${{ always() }}
    steps:
      - name: Delete repo copy and conda env
--- a/.github/workflows/chipyard-run-tests.yml
+++ b/.github/workflows/chipyard-run-tests.yml
@@ -62,32 +62,11 @@ jobs:
              - '**/.gitignore'
              - '.github/ISSUE_TEMPLATE/**'

-  create-conda-env-jktgz:
-    name: create-conda-env-jktgz
+  create-conda-env-as4:
+    name: create-conda-env-as4
    needs: [change-filters, cancel-prior-workflows]
    if: needs.change-filters.outputs.needs-rtl == 'true'
-    runs-on: jktgz
-    steps:
-      - name: Delete old checkout
-        run: |
-            ls -alh .
-            rm -rf ${{ github.workspace }}/* || true
-            rm -rf ${{ github.workspace }}/.* || true
-            ls -alh .
-      - name: Checkout
-        uses: actions/checkout@v3
-      - name: Git workaround
-        uses: ./.github/actions/git-workaround
-      - name: Cleanup conda
-        uses: ./.github/actions/cleanup-conda
-      - name: Create conda env
-        uses: ./.github/actions/create-conda-env
-
-  create-conda-env-jktqos:
-    name: create-conda-env-jktqos
-    needs: [change-filters, cancel-prior-workflows]
-    if: needs.change-filters.outputs.needs-rtl == 'true'
-    runs-on: jktqos
+    runs-on: as4
    steps:
      - name: Delete old checkout
        run: |
@@ -109,7 +88,7 @@ jobs:
  # When adding new prep jobs, please add them to `needs` below
  setup-complete:
    name: setup-complete
-    needs: [create-conda-env-jktgz, create-conda-env-jktqos]
+    needs: [create-conda-env-as4]
    runs-on: ubuntu-latest
    steps:
      - name: Set up complete
@@ -121,7 +100,7 @@ jobs:
    name: commit-on-master-check
    needs: [setup-complete]
    if: needs.change-filters.outputs.needs-rtl == 'true'
-    runs-on: self-hosted
+    runs-on: as4
    steps:
      - name: Delete old checkout
        run: |
@@ -144,7 +123,7 @@ jobs:
    name: tutorial-setup-check
    needs: [setup-complete]
    if: needs.change-filters.outputs.needs-rtl == 'true'
-    runs-on: self-hosted
+    runs-on: as4
    steps:
      - name: Delete old checkout
        run: |
@@ -166,7 +145,7 @@ jobs:
  documentation-check:
    name: documentation-check
    needs: [setup-complete]
-    runs-on: self-hosted
+    runs-on: as4
    steps:
      - name: Delete old checkout
        run: |
@@ -192,7 +171,7 @@ jobs:
    name: build-extra-tests
    needs: [setup-complete]
    if: needs.change-filters.outputs.needs-rtl == 'true'
-    runs-on: self-hosted
+    runs-on: as4
    steps:
      - name: Delete old checkout
        run: |
@@ -224,7 +203,7 @@ jobs:
  prepare-chipyard-cores:
    name: prepare-chipyard-cores
    needs: setup-complete
-    runs-on: self-hosted
+    runs-on: as4
    steps:
      - name: Delete old checkout
        run: |
@@ -246,7 +225,7 @@ jobs:
  prepare-chipyard-constellation:
    name: prepare-chipyard-constellation
    needs: setup-complete
-    runs-on: self-hosted
+    runs-on: as4
    steps:
      - name: Delete old checkout
        run: |
@@ -268,7 +247,7 @@ jobs:
  prepare-chipyard-peripherals:
    name: prepare-chipyard-peripherals
    needs: setup-complete
-    runs-on: self-hosted
+    runs-on: as4
    steps:
      - name: Delete old checkout
        run: |
@@ -290,7 +269,7 @@ jobs:
  prepare-chipyard-accels:
    name: prepare-chipyard-accels
    needs: setup-complete
-    runs-on: self-hosted
+    runs-on: as4
    steps:
      - name: Delete old checkout
        run: |
@@ -312,7 +291,7 @@ jobs:
  prepare-chipyard-tracegen:
    name: prepare-chipyard-tracegen
    needs: setup-complete
-    runs-on: self-hosted
+    runs-on: as4
    steps:
      - name: Delete old checkout
        run: |
@@ -334,7 +313,7 @@ jobs:
  prepare-chipyard-other:
    name: prepare-chipyard-other
    needs: setup-complete
-    runs-on: self-hosted
+    runs-on: as4
    steps:
      - name: Delete old checkout
        run: |
@@ -356,7 +335,7 @@ jobs:
  prepare-chipyard-fpga:
    name: prepare-chipyard-fpga
    needs: setup-complete
-    runs-on: self-hosted
+    runs-on: as4
    steps:
      - name: Delete old checkout
        run: |
@@ -381,7 +360,7 @@ jobs:
  chipyard-spike-gemmini-run-tests:
    name: chipyard-spike-gemmini-run-tests
    needs: prepare-chipyard-accels # technically doesn't depend on RTL but should be after the build.sh for Gemmini
-    runs-on: jktqos
+    runs-on: as4
    steps:
      - name: Delete old checkout
        run: |
@@ -410,7 +389,7 @@ jobs:
  chipyard-rocket-run-tests:
    name: chipyard-rocket-run-tests
    needs: prepare-chipyard-cores
-    runs-on: self-hosted
+    runs-on: as4
    steps:
      - name: Delete old checkout
        run: |
@@ -433,7 +412,7 @@ jobs:
  chipyard-prefetchers-run-tests:
    name: chipyard-prefetchers-run-tests
    needs: prepare-chipyard-cores
-    runs-on: self-hosted
+    runs-on: as4
    steps:
      - name: Delete old checkout
        run: |
@@ -456,7 +435,7 @@ jobs:
  chipyard-hetero-run-tests:
    name: chipyard-hetero-run-tests
    needs: prepare-chipyard-cores
-    runs-on: self-hosted
+    runs-on: as4
    steps:
      - name: Delete old checkout
        run: |
@@ -479,7 +458,7 @@ jobs:
  chipyard-boom-run-tests:
    name: chipyard-boom-run-tests
    needs: prepare-chipyard-cores
-    runs-on: self-hosted
+    runs-on: as4
    steps:
      - name: Delete old checkout
        run: |
@@ -502,7 +481,7 @@ jobs:
  chipyard-shuttle-run-tests:
    name: chipyard-shuttle-run-tests
    needs: prepare-chipyard-cores
-    runs-on: self-hosted
+    runs-on: as4
    steps:
      - name: Delete old checkout
        run: |
@@ -525,7 +504,7 @@ jobs:
  chipyard-cva6-run-tests:
    name: chipyard-cva6-run-tests
    needs: prepare-chipyard-cores
-    runs-on: self-hosted
+    runs-on: as4
    steps:
      - name: Delete old checkout
        run: |
@@ -548,7 +527,7 @@ jobs:
  chipyard-ibex-run-tests:
    name: chipyard-ibex-run-tests
    needs: prepare-chipyard-cores
-    runs-on: self-hosted
+    runs-on: as4
    steps:
      - name: Delete old checkout
        run: |
@@ -571,7 +550,7 @@ jobs:
  chipyard-sodor-run-tests:
    name: chipyard-sodor-run-tests
    needs: prepare-chipyard-cores
-    runs-on: self-hosted
+    runs-on: as4
    steps:
      - name: Delete old checkout
        run: |
@@ -594,7 +573,7 @@ jobs:
  chipyard-spike-run-tests:
    name: chipyard-spike-run-tests
    needs: prepare-chipyard-cores
-    runs-on: self-hosted
+    runs-on: as4
    steps:
      - name: Delete old checkout
        run: |
@@ -617,7 +596,7 @@ jobs:
  chipyard-dmirocket-run-tests:
    name: chipyard-dmirocket-run-tests
    needs: prepare-chipyard-peripherals
-    runs-on: self-hosted
+    runs-on: as4
    steps:
      - name: Delete old checkout
        run: |
@@ -640,7 +619,7 @@ jobs:
  chipyard-dmiboom-run-tests:
    name: chipyard-dmiboom-run-tests
    needs: prepare-chipyard-peripherals
-    runs-on: self-hosted
+    runs-on: as4
    steps:
      - name: Delete old checkout
        run: |
@@ -663,7 +642,7 @@ jobs:
  chipyard-spiflashwrite-run-tests:
    name: chipyard-spiflashwrite-run-tests
    needs: prepare-chipyard-peripherals
-    runs-on: self-hosted
+    runs-on: as4
    steps:
      - name: Delete old checkout
        run: |
@@ -686,7 +665,7 @@ jobs:
  chipyard-manyperipherals-run-tests:
    name: chipyard-manyperipherals-run-tests
    needs: prepare-chipyard-peripherals
-    runs-on: self-hosted
+    runs-on: as4
    steps:
      - name: Delete old checkout
        run: |
@@ -709,7 +688,7 @@ jobs:
  chipyard-tethered-run-tests:
    name: chipyard-tethered-run-tests
    needs: prepare-chipyard-peripherals
-    runs-on: self-hosted
+    runs-on: as4
    steps:
      - name: Delete old checkout
        run: |
@@ -732,7 +711,7 @@ jobs:
  chipyard-sha3-run-tests:
    name: chipyard-sha3-run-tests
    needs: prepare-chipyard-accels
-    runs-on: self-hosted
+    runs-on: as4
    steps:
      - name: Delete old checkout
        run: |
@@ -755,7 +734,7 @@ jobs:
  chipyard-gemmini-run-tests:
    name: chipyard-gemmini-run-tests
    needs: prepare-chipyard-accels
-    runs-on: self-hosted
+    runs-on: as4
    steps:
      - name: Delete old checkout
        run: |
@@ -778,7 +757,7 @@ jobs:
  chipyard-manymmioaccels-run-tests:
    name: chipyard-manymmioaccels-run-tests
    needs: prepare-chipyard-accels
-    runs-on: self-hosted
+    runs-on: as4
    steps:
      - name: Delete old checkout
        run: |
@@ -801,7 +780,7 @@ jobs:
  # chipyard-nvdla-run-tests:
  #   name: chipyard-nvdla-run-tests
  #   needs: prepare-chipyard-accels
-  #   runs-on: self-hosted
+  #   runs-on: as4
  #   steps:
  #     - name: Delete old checkout
  #       run: |
@@ -824,7 +803,7 @@ jobs:
  chipyard-mempress-run-tests:
    name: chipyard-mempress-run-tests
    needs: prepare-chipyard-accels
-    runs-on: self-hosted
+    runs-on: as4
    steps:
      - name: Delete old checkout
        run: |
@@ -848,7 +827,7 @@ jobs:
  tracegen-boom-run-tests:
    name: tracegen-boom-run-tests
    needs: prepare-chipyard-tracegen
-    runs-on: self-hosted
+    runs-on: as4
    steps:
      - name: Delete old checkout
        run: |
@@ -871,7 +850,7 @@ jobs:
  tracegen-run-tests:
    name: tracegen-run-tests
    needs: prepare-chipyard-tracegen
-    runs-on: self-hosted
+    runs-on: as4
    steps:
      - name: Delete old checkout
        run: |
@@ -894,7 +873,7 @@ jobs:
  icenet-run-tests:
    name: icenet-run-tests
    needs: prepare-chipyard-other
-    runs-on: self-hosted
+    runs-on: as4
    steps:
      - name: Delete old checkout
        run: |
@@ -917,7 +896,7 @@ jobs:
  testchipip-run-tests:
    name: testchipip-run-tests
    needs: prepare-chipyard-other
-    runs-on: self-hosted
+    runs-on: as4
    steps:
      - name: Delete old checkout
        run: |
@@ -940,7 +919,7 @@ jobs:
  rocketchip-run-tests:
    name: rocketchip-run-tests
    needs: prepare-chipyard-other
-    runs-on: self-hosted
+    runs-on: as4
    steps:
      - name: Delete old checkout
        run: |
@@ -979,7 +958,7 @@ jobs:
  constellation-run-tests:
    name: constellation-run-tests
    needs: prepare-chipyard-other
-    runs-on: self-hosted
+    runs-on: as4
    steps:
      - name: Delete old checkout
        run: |
@@ -1002,7 +981,7 @@ jobs:
  chipyard-constellation-run-tests:
    name: chipyard-constellation-run-tests
    needs: prepare-chipyard-constellation
-    runs-on: self-hosted
+    runs-on: as4
    steps:
      - name: Delete old checkout
        run: |
@@ -1026,7 +1005,7 @@ jobs:
  firesim-run-tests:
    name: firesim-run-tests
    needs: setup-complete
-    runs-on: self-hosted
+    runs-on: as4
    steps:
      - name: Delete old checkout
        run: |
@@ -1050,7 +1029,7 @@ jobs:
  fireboom-run-tests:
    name: fireboom-run-tests
    needs: setup-complete
-    runs-on: self-hosted
+    runs-on: as4
    steps:
      - name: Delete old checkout
        run: |
--- a/.github/workflows/update-circt.yml
+++ b/.github/workflows/update-circt.yml
@@ -0,0 +1,25 @@
+name: update-circt
+
+# run daily
+on:
+  schedule:
+    - cron: 0,15,30,45 * * * *
+    #- cron: 0 8 * * *
+
+defaults:
+  run:
+    shell: bash -leo pipefail {0}
+
+jobs:
+  update-circt:
+    name: update-circt
+    runs-on: ubuntu-latest
+    steps:
+      - name: Update CIRCT
+        uses: circt/update-circt@v1.0.0
+        with:
+          user: 'bartender'
+          email: 'firesimchipyard@gmail.com'
+          pr-reviewers: ''
+          pr-labels: 'changelog:changed'
+          circt-config: './conda-reqs/circt.json'
--- a/.gitmodules
+++ b/.gitmodules
@@ -133,3 +133,12 @@
 [submodule "generators/hardfloat"]
 	path = generators/hardfloat
 	url = https://github.com/ucb-bar/berkeley-hardfloat.git
+[submodule "generators/caliptra-aes-acc"]
+	path = generators/caliptra-aes-acc
+	url = https://github.com/ucb-bar/caliptra-aes-acc
+[submodule "generators/rocc-acc-utils"]
+	path = generators/rocc-acc-utils
+	url = https://github.com/ucb-bar/rocc-acc-utils
+[submodule "tools/install-circt"]
+	path = tools/install-circt
+	url = https://github.com/circt/install-circt/
--- a/README.md
+++ b/README.md
@@ -85,7 +85,7 @@ These additional publications cover many of the internal components used in Chip

 ## Acknowledgements

-This work is supported by the NSF CCRI ENS Chipyard Award #201662.
+This work is supported by the NSF CCRI ENS Chipyard Award #2016662.

 [hwacha]:https://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-262.pdf
 [hammer]:https://github.com/ucb-bar/hammer
--- a/build.sbt
+++ b/build.sbt
@@ -150,7 +150,7 @@ lazy val chipyard = (project in file("generators/chipyard"))
    sha3, // On separate line to allow for cleaner tutorial-setup patches
    dsptools, rocket_dsp_utils,
    gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
-    constellation, mempress, barf, shuttle)
+    constellation, mempress, barf, shuttle, caliptra_aes)
  .settings(libraryDependencies ++= rocketLibDeps.value)
  .settings(
    libraryDependencies ++= Seq(
@@ -234,6 +234,16 @@ lazy val nvdla = (project in file("generators/nvdla"))
  .settings(libraryDependencies ++= rocketLibDeps.value)
  .settings(commonSettings)

+lazy val caliptra_aes = (project in file("generators/caliptra-aes-acc"))
+  .dependsOn(rocketchip, rocc_acc_utils, testchipip, midasTargetUtils)
+  .settings(libraryDependencies ++= rocketLibDeps.value)
+  .settings(commonSettings)
+
+lazy val rocc_acc_utils = (project in file("generators/rocc-acc-utils"))
+  .dependsOn(rocketchip)
+  .settings(libraryDependencies ++= rocketLibDeps.value)
+  .settings(commonSettings)
+
 lazy val iocell = Project(id = "iocell", base = file("./tools/barstools/") / "iocell")
  .settings(chiselSettings)
  .settings(commonSettings)
--- a/common.mk
+++ b/common.mk
@@ -119,12 +119,12 @@ $(BOOTROM_TARGETS): $(build_dir)/bootrom.%.img: $(TESTCHIP_RSRCS_DIR)/testchipip
 #########################################################################################
 # compile scala jars
 #########################################################################################
-$(CHIPYARD_CLASSPATH_TARGETS) &: $(CHIPYARD_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS)
+$(CHIPYARD_CLASSPATH_TARGETS) &: $(CHIPYARD_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(CHIPYARD_VLOG_SOURCES)
 	mkdir -p $(dir $@)
 	$(call run_sbt_assembly,$(SBT_PROJECT),$(CHIPYARD_CLASSPATH))

 # order only dependency between sbt runs needed to avoid concurrent sbt runs
-$(TAPEOUT_CLASSPATH_TARGETS) &: $(BARSTOOLS_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) | $(CHIPYARD_CLASSPATH_TARGETS)
+$(TAPEOUT_CLASSPATH_TARGETS) &: $(BARSTOOLS_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(BARSTOOLS_VLOG_SOURCES) | $(CHIPYARD_CLASSPATH_TARGETS)
 	mkdir -p $(dir $@)
 	$(call run_sbt_assembly,tapeout,$(TAPEOUT_CLASSPATH))

@@ -227,7 +227,7 @@ $(FINAL_ANNO_FILE): $(EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE) $(SFC_LEVEL)
 	touch $@

 $(SFC_MFC_TARGETS) &: private TMP_DIR := $(shell mktemp -d -t cy-XXXXXXXX)
-$(SFC_MFC_TARGETS) &: $(TAPEOUT_CLASSPATH_TARGETS) $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS) $(MFC_LOWERING_OPTIONS) $(CHIPYARD_VLOG_SOURCES) $(BARSTOOLS_VLOG_SOURCES)
+$(SFC_MFC_TARGETS) &: $(TAPEOUT_CLASSPATH_TARGETS) $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS) $(MFC_LOWERING_OPTIONS)
 	rm -rf $(GEN_COLLATERAL_DIR)
 	$(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),barstools.tapeout.transforms.GenerateModelStageMain,\
 		--no-dedup \
@@ -246,9 +246,7 @@ $(SFC_MFC_TARGETS) &: $(TAPEOUT_CLASSPATH_TARGETS) $(FIRRTL_FILE) $(FINAL_ANNO_F
 	@if [ $(shell cat $(SFC_LEVEL)) = low ]; then cat $(TMP_DIR)/unnec-anno-deleted2.sfc.anno.json > $(SFC_ANNO_FILE) && rm $(TMP_DIR)/unnec-anno-deleted.sfc.anno.json && rm $(TMP_DIR)/unnec-anno-deleted2.sfc.anno.json; fi
 	firtool \
 		--format=fir \
-		--dedup \
 		--export-module-hierarchy \
-		--emit-metadata \
 		--verify-each=true \
 		--warn-on-unprocessed-annotations \
 		--disable-annotation-classless \
@@ -257,13 +255,13 @@ $(SFC_MFC_TARGETS) &: $(TAPEOUT_CLASSPATH_TARGETS) $(FIRRTL_FILE) $(FINAL_ANNO_F
 		--lowering-options=$(shell cat $(MFC_LOWERING_OPTIONS)) \
 		--repl-seq-mem \
 		--repl-seq-mem-file=$(MFC_SMEMS_CONF) \
-		--repl-seq-mem-circuit=$(MODEL) \
 		--annotation-file=$(SFC_ANNO_FILE) \
 		--split-verilog \
 		-o $(GEN_COLLATERAL_DIR) \
 		$(SFC_FIRRTL_FILE)
 	-mv $(SFC_SMEMS_CONF) $(MFC_SMEMS_CONF) 2> /dev/null
 	$(SED) -i 's/.*/& /' $(MFC_SMEMS_CONF) # need trailing space for SFC macrocompiler
+	touch $(MFC_BB_MODS_FILELIST) # if there are no BB's then the file might not be generated, instead always generate it
 # DOC include end: FirrtlCompiler

 $(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(ALL_MODS_FILELIST) $(BB_MODS_FILELIST) $(MFC_MODEL_HRCHY_JSON_UNIQUIFIED) &: $(MFC_MODEL_HRCHY_JSON) $(MFC_TOP_HRCHY_JSON) $(MFC_FILELIST) $(MFC_BB_MODS_FILELIST)
--- a/conda-reqs/chipyard.yaml
+++ b/conda-reqs/chipyard.yaml
@@ -29,7 +29,7 @@ dependencies:
    - conda-gcc-specs
    - binutils

-    - firtool==1.30.0 # from ucb-bar channel - https://github.com/ucb-bar/firtool-feedstock
+    # firtool handled outside of conda

    # misc
    - autoconf
@@ -102,7 +102,7 @@ dependencies:
    - sty
    - open_pdks.sky130a
    - pip:
-        - hammer-vlsi[asap7]==1.1.2
+        - hammer-vlsi[asap7]==1.2.0

    # doc requirements
    - sphinx
--- a/conda-reqs/circt.json
+++ b/conda-reqs/circt.json
@@ -0,0 +1,3 @@
+{
+  "version": "firtool-1.60.0"
+}
--- a/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml
+++ b/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml
--- a/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml
+++ b/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml
--- a/docs/Customization/Boot-Process.rst
+++ b/docs/Customization/Boot-Process.rst
@@ -12,7 +12,7 @@ Device Tree Binary (dtb) which details the components of the system.
 The assembly for the BootROM code is located in
 `generators/testchipip/src/main/resources/testchipip/bootrom/bootrom.S <https://github.com/ucb-bar/testchipip/blob/master/src/main/resources/testchipip/bootrom/bootrom.S>`_.
 The BootROM address space starts at ``0x10000`` (determined by the ``BootROMParams`` key in the configuration) and execution starts at address
-``0x10040`` (given by the linker script and reset vector in the ``BootROMParams``), which is marked by the ``_hang`` label in the BootROM assembly.
+``0x10000`` (given by the linker script and reset vector in the ``BootROMParams``), which is marked by the ``_hang`` label in the BootROM assembly.

 The Chisel generator encodes the assembled instructions into the BootROM
 hardware at elaboration time, so if you want to change the BootROM code, you
--- a/docs/Customization/Incorporating-Verilog-Blocks.rst
+++ b/docs/Customization/Incorporating-Verilog-Blocks.rst
@@ -161,4 +161,31 @@ transformed or augmented by any Chipyard FIRRTL transform.
 As mentioned earlier in this section, ``BlackBox`` resource files must
 be integrated into the build process, so any project providing
 ``BlackBox`` resources must be made visible to the ``tapeout`` project
-in ``build.sbt``
+in ``build.sbt``.
+
+Differences between ``HasBlackBoxPath`` and ``HasBlackBoxResource``
+-------------------------------------------------------------------
+
+Chisel provides two mechanisms for integrating blackbox files into a Chisel project that work slightly differently in Chipyard: ``HasBlackBoxPath`` and ``HasBlackBoxResource``.
+
+``HasBlackBoxResource`` incorporates extra files by looking up the relative path of the files within the ``src/main/resources`` area of project.
+This requires that the file added by ``addResource`` is present in the ``src/main/resources`` area and is **not** auto-generated (the file is static throughout the lifetime of generating RTL).
+This is due to the fact that when the Chisel sources are compiled they are put in a ``jar`` file, along with the ``src/main/resources`` area, and that ``jar`` is used to run the Chisel generator.
+Files referenced by the ``addResource`` must be located within this ``jar`` file during the Chisel elaboration.
+Thus if a file is generated during Chisel generation it will not be present in the ``jar`` file until the next time the Chisel sources are compiled.
+
+``HasBlackBoxPath`` differs in that it incorporates extra files by using an absolute path to them.
+Later in the build process, the FIRRTL compiler will copy the file from that location to the generated sources directory.
+Thus, the file must be present before the FIRRTL compiler is run (i.e. the file doesn't need to be in the ``src/main/resources`` or it can be auto-generated during Chisel elaboration).
+
+Additionally, both mechanisms do not enforce the order of files added.
+For example:
+
+.. code-block:: scala
+
+    addResource("fileA")
+    addResource("fileB")
+
+In this case, ``fileA`` is not guaranteed to be before ``fileB`` when passed to downstream tools.
+To bypass this, it is recommended to auto-generate a single file with the ordering needed by concatenating the files and using ``addPath`` given by ``HasBlackBoxPath``.
+An example of this is https://github.com/ucb-bar/ibex-wrapper/blob/main/src/main/scala/IbexCoreBlackbox.scala.
--- a/docs/Customization/Memory-Hierarchy.rst
+++ b/docs/Customization/Memory-Hierarchy.rst
@@ -97,7 +97,7 @@ and remove the off-chip link. This is done by adding a fragment like
 ``testchipip.WithScratchpad`` to your configuration and removing the
 memory port with ``freechips.rocketchip.subsystem.WithNoMemPort``.

-.. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala
+.. literalinclude:: ../../generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala
    :language: scala
    :start-after: DOC include start: mbusscratchpadrocket
    :end-before: DOC include end: mbusscratchpadrocket
--- a/docs/Prototyping/Arty.rst
+++ b/docs/Prototyping/Arty.rst
@@ -34,7 +34,7 @@ Probe an address on the target system:

 .. code-block:: shell

-		./uart_tsi +tty=/dev/ttyUSBX +init_read=0x10040 none
+		./uart_tsi +tty=/dev/ttyUSBX +init_read=0x10000 none

 Write some address before running a program:

--- a/docs/Prototyping/NexysVideo.rst
+++ b/docs/Prototyping/NexysVideo.rst
@@ -34,7 +34,7 @@ Probe an address on the target system:

 .. code-block:: shell

-		./uart_tsi +tty=/dev/ttyUSBX +init_read=0x10040 none
+		./uart_tsi +tty=/dev/ttyUSBX +init_read=0x10000 none

 Write some address before running a program:

--- a/docs/Simulation/Software-RTL-Simulation.rst
+++ b/docs/Simulation/Software-RTL-Simulation.rst
@@ -81,6 +81,24 @@ For example:

 .. _sw-sim-custom:

+Custom Benchmarks/Tests
+-------------------------------
+
+To compile your own bare-metal code to run in a Verilator/VCS simulation, add it to Chipyard's ``tests`` directory then add its name to the list of ``PROGRAMS`` inside the ``Makefile``. These binaries are compiled with the libgloss-htif library, which implements a minimal set of useful syscalls for bare-metal binaries. Then when you run ``make``, all of the programs inside ``tests`` will be compiled into ``.riscv`` ELF binaries, which can be used with the simulator as described above.
+
+.. code-block:: shell
+
+    # Enter Tests directory
+    cd tests
+    make
+
+    # Enter Verilator or VCS directory
+    cd ../sims/verilator
+    make run-binary BINARY=../../tests/hello.riscv
+
+.. Note:: On multi-core configurations, only hart (**har**\ dware **t**\ hread) 0 executes the ``main()`` function. All other harts execute the secondary ``__main()`` function, which defaults to a busy loop. To run a multi-threaded workload on a Verilator/VCS simulation, override ``__main()`` with your own code. More details can be found `here <https://github.com/ucb-bar/libgloss-htif>`_
+
+
 Makefile Variables and Commands
 -------------------------------
 You can get a list of useful Makefile variables and commands available from the Verilator or VCS directories. simply run ``make help``:
--- a/docs/VLSI/Sky130-Commercial-Tutorial.rst
+++ b/docs/VLSI/Sky130-Commercial-Tutorial.rst
@@ -60,7 +60,7 @@ The prerequisite setup for this tutorial may eventually be scripted, but for now
 .. code-block:: shell

    # download all files for Sky130A PDK
-    conda create -c litex-hub --prefix ~/.conda-sky130 open_pdks.sky130a=1.0.399_0_g63dbde9
+    conda create -c litex-hub --prefix ~/.conda-sky130 open_pdks.sky130a=1.0.457_0_g32e8f23
    # clone the SRAM22 Sky130 SRAM macros
    git clone https://github.com/rahulk29/sram22_sky130_macros ~/sram22_sky130_macros

--- a/docs/VLSI/Sky130-OpenROAD-Tutorial.rst
+++ b/docs/VLSI/Sky130-OpenROAD-Tutorial.rst
@@ -73,7 +73,7 @@ Note that we create a new conda environment for each tool because some of them h
    conda config --add channels defaults

    # download all files for Sky130A PDK
-    conda create -c litex-hub --prefix ~/.conda-sky130 open_pdks.sky130a=1.0.399_0_g63dbde9
+    conda create -c litex-hub --prefix ~/.conda-sky130 open_pdks.sky130a=1.0.457_0_g32e8f23
    # clone the SRAM22 Sky130 SRAM macros
    git clone https://github.com/rahulk29/sram22_sky130_macros ~/sram22_sky130_macros

--- a/fpga/Makefile
+++ b/fpga/Makefile
@@ -72,11 +72,11 @@ ifeq ($(SUB_PROJECT),nexysvideo)
 	FPGA_BRAND        ?= xilinx
 endif

-ifeq ($(SUB_PROJECT),arty)
+ifeq ($(SUB_PROJECT),arty35t)
 	# TODO: Fix with Arty
 	SBT_PROJECT       ?= fpga_platforms
-	MODEL             ?= ArtyFPGATestHarness
-	VLOG_MODEL        ?= ArtyFPGATestHarness
+	MODEL             ?= Arty35THarness
+	VLOG_MODEL        ?= Arty35THarness
 	MODEL_PACKAGE     ?= chipyard.fpga.arty
 	CONFIG            ?= TinyRocketArtyConfig
 	CONFIG_PACKAGE    ?= chipyard.fpga.arty
--- a/fpga/src/main/scala/arty/HarnessBinders.scala
+++ b/fpga/src/main/scala/arty/HarnessBinders.scala
@@ -15,19 +15,19 @@ import chipyard.harness.{HarnessBinder}
 import chipyard.iobinders._

 class WithArtyDebugResetHarnessBinder extends HarnessBinder({
-  case (th: ArtyFPGATestHarness, port: DebugResetPort) => {
+  case (th: Arty35THarness, port: DebugResetPort) => {
    th.dut_ndreset := port.io // Debug module reset
  }
 })

 class WithArtyJTAGResetHarnessBinder extends HarnessBinder({
-  case (th: ArtyFPGATestHarness, port: JTAGResetPort) => {
+  case (th: Arty35THarness, port: JTAGResetPort) => {
    port.io := PowerOnResetFPGAOnly(th.clock_32MHz) // JTAG module reset
  }
 })

 class WithArtyJTAGHarnessBinder extends HarnessBinder({
-  case (th: ArtyFPGATestHarness, port: JTAGPort) => {
+  case (th: Arty35THarness, port: JTAGPort) => {
    val jtag_wire = Wire(new JTAGIO)
    jtag_wire.TDO.data := port.io.TDO
    jtag_wire.TDO.driven := true.B
@@ -62,7 +62,7 @@ class WithArtyJTAGHarnessBinder extends HarnessBinder({
 })

 class WithArtyUARTHarnessBinder extends HarnessBinder({
-  case (th: ArtyFPGATestHarness, port: UARTPort) => {
+  case (th: Arty35THarness, port: UARTPort) => {
    withClockAndReset(th.clock_32MHz, th.ck_rst) {
      IOBUF(th.uart_rxd_out,  port.io.txd)
      port.io.rxd := IOBUF(th.uart_txd_in)
--- a/fpga/src/main/scala/arty/IOBinders.scala
+++ b/fpga/src/main/scala/arty/IOBinders.scala
@@ -18,6 +18,6 @@ class WithDebugResetPassthrough extends ComposeIOBinder({
    val io_sjtag_reset: Bool = IO(Input(Bool())).suggestName("sjtag_reset")
    sjtag.reset := io_sjtag_reset

-    (Seq(DebugResetPort(io_ndreset), JTAGResetPort(io_sjtag_reset)), Nil)
+    (Seq(DebugResetPort(() => io_ndreset), JTAGResetPort(() => io_sjtag_reset)), Nil)
  }
 })
--- a/fpga/src/main/scala/arty/TestHarness.scala
+++ b/fpga/src/main/scala/arty/TestHarness.scala
@@ -9,9 +9,8 @@ import org.chipsalliance.cde.config.{Parameters}
 import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell}

 import chipyard.harness.{HasHarnessInstantiators}
-import chipyard.iobinders.{HasIOBinders}

-class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessInstantiators {
+class Arty35THarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessInstantiators {
  // Convert harness resets from Bool to Reset type.
  val hReset = Wire(Reset())
  hReset := ~ck_rst
--- a/fpga/src/main/scala/arty100t/Configs.scala
+++ b/fpga/src/main/scala/arty100t/Configs.scala
@@ -21,18 +21,19 @@ class WithNoDesignKey extends Config((site, here, up) => {
  case DesignKey => (p: Parameters) => new SimpleLazyRawModule()(p)
 })

-class WithArty100TTweaks extends Config(
+class WithArty100TTweaks(freqMHz: Double = 50) extends Config(
  new WithArty100TUARTTSI ++
  new WithArty100TDDRTL ++
  new WithNoDesignKey ++
  new testchipip.WithUARTTSIClient ++
  new chipyard.harness.WithSerialTLTiedOff ++
-  new chipyard.harness.WithHarnessBinderClockFreqMHz(50) ++
-  new chipyard.config.WithMemoryBusFrequency(50.0) ++
-  new chipyard.config.WithFrontBusFrequency(50.0) ++
-  new chipyard.config.WithSystemBusFrequency(50.0) ++
-  new chipyard.config.WithPeripheryBusFrequency(50.0) ++
-  new chipyard.config.WithControlBusFrequency(50.0) ++
+  new chipyard.harness.WithHarnessBinderClockFreqMHz(freqMHz) ++
+  new chipyard.config.WithMemoryBusFrequency(freqMHz) ++
+  new chipyard.config.WithFrontBusFrequency(freqMHz) ++
+  new chipyard.config.WithSystemBusFrequency(freqMHz) ++
+  new chipyard.config.WithPeripheryBusFrequency(freqMHz) ++
+  new chipyard.config.WithControlBusFrequency(freqMHz) ++
+  new chipyard.config.WithOffchipBusFrequency(freqMHz) ++
  new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
  new chipyard.clocking.WithPassthroughClockGenerator ++
  new chipyard.config.WithNoDebug ++ // no jtag
@@ -46,23 +47,14 @@ class RocketArty100TConfig extends Config(
  new chipyard.config.WithBroadcastManager ++ // no l2
  new chipyard.RocketConfig)

-class UART230400RocketArty100TConfig extends Config(
-  new WithArty100TUARTTSI(uartBaudRate = 230400) ++
-  new RocketArty100TConfig)
-
-class UART460800RocketArty100TConfig extends Config(
-  new WithArty100TUARTTSI(uartBaudRate = 460800) ++
-  new RocketArty100TConfig)
-
-class UART921600RocketArty100TConfig extends Config(
-  new WithArty100TUARTTSI(uartBaudRate = 921600) ++
-  new RocketArty100TConfig)
-
-
 class NoCoresArty100TConfig extends Config(
  new WithArty100TTweaks ++
-  new chipyard.config.WithMemoryBusFrequency(50.0) ++
-  new chipyard.config.WithPeripheryBusFrequency(50.0) ++  // Match the sbus and pbus frequency
-  new chipyard.config.WithControlBusFrequency(50.0) ++
  new chipyard.config.WithBroadcastManager ++ // no l2
  new chipyard.NoCoresConfig)
+
+// This will fail to close timing above 50 MHz
+class BringupArty100TConfig extends Config(
+  new WithArty100TSerialTLToGPIO ++
+  new WithArty100TTweaks(freqMHz = 50) ++
+  new testchipip.WithSerialTLClockDirection(provideClockFreqMHz = Some(50)) ++
+  new chipyard.ChipBringupHostConfig)
--- a/fpga/src/main/scala/arty100t/Harness.scala
+++ b/fpga/src/main/scala/arty100t/Harness.scala
@@ -17,7 +17,6 @@ import sifive.blocks.devices.uart._

 import chipyard._
 import chipyard.harness._
-import chipyard.iobinders.{HasIOBinders}

 class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell {
  def dp = designParameters
--- a/fpga/src/main/scala/arty100t/HarnessBinders.scala
+++ b/fpga/src/main/scala/arty100t/HarnessBinders.scala
@@ -1,6 +1,7 @@
 package chipyard.fpga.arty100t

 import chisel3._
+import chisel3.experimental.{DataMirror, Direction}

 import freechips.rocketchip.jtag.{JTAGIO}
 import freechips.rocketchip.subsystem.{PeripheryBusKey}
@@ -11,16 +12,17 @@ import freechips.rocketchip.diplomacy.{LazyRawModuleImp}
 import sifive.blocks.devices.uart.{UARTPortIO, HasPeripheryUARTModuleImp, UARTParams}
 import sifive.blocks.devices.jtag.{JTAGPins, JTAGPinsFromPort}
 import sifive.blocks.devices.pinctrl.{BasePin}
-
-import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly}
-
+import sifive.fpgashells.shell._
+import sifive.fpgashells.ip.xilinx._
+import sifive.fpgashells.shell.xilinx._
+import sifive.fpgashells.clocks._
 import chipyard._
 import chipyard.harness._
 import chipyard.iobinders._

 import testchipip._

-class WithArty100TUARTTSI(uartBaudRate: BigInt = 115200) extends HarnessBinder({
+class WithArty100TUARTTSI extends HarnessBinder({
  case (th: HasHarnessInstantiators, port: UARTTSIPort) => {
    val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
    ath.io_uart_bb.bundle <> port.io.uart
@@ -41,3 +43,43 @@ class WithArty100TDDRTL extends HarnessBinder({
    ddrClientBundle <> port.io
  }
 })
+
+// Uses PMOD JA/JB
+class WithArty100TSerialTLToGPIO extends HarnessBinder({
+  case (th: HasHarnessInstantiators, port: SerialTLPort) => {
+    val artyTh = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
+    val harnessIO = IO(chiselTypeOf(port.io)).suggestName("serial_tl")
+    harnessIO <> port.io
+    val clkIO = IOPin(harnessIO.clock)
+    val packagePinsWithPackageIOs = Seq(
+      ("G13", clkIO),
+      ("B11", IOPin(harnessIO.bits.out.valid)),
+      ("A11", IOPin(harnessIO.bits.out.ready)),
+      ("D12", IOPin(harnessIO.bits.in.valid)),
+      ("D13", IOPin(harnessIO.bits.in.ready)),
+      ("B18", IOPin(harnessIO.bits.out.bits, 0)),
+      ("A18", IOPin(harnessIO.bits.out.bits, 1)),
+      ("K16", IOPin(harnessIO.bits.out.bits, 2)),
+      ("E15", IOPin(harnessIO.bits.out.bits, 3)),
+      ("E16", IOPin(harnessIO.bits.in.bits, 0)),
+      ("D15", IOPin(harnessIO.bits.in.bits, 1)),
+      ("C15", IOPin(harnessIO.bits.in.bits, 2)),
+      ("J17", IOPin(harnessIO.bits.in.bits, 3))
+    )
+    packagePinsWithPackageIOs foreach { case (pin, io) => {
+      artyTh.xdc.addPackagePin(io, pin)
+      artyTh.xdc.addIOStandard(io, "LVCMOS33")
+    }}
+
+    // Don't add IOB to the clock, if its an input
+    if (DataMirror.directionOf(port.io.clock) == Direction.Input) {
+      packagePinsWithPackageIOs foreach { case (pin, io) => {
+        artyTh.xdc.addIOB(io)
+      }}
+    }
+
+    artyTh.sdc.addClock("ser_tl_clock", clkIO, 100)
+    artyTh.sdc.addGroup(pins = Seq(clkIO))
+    artyTh.xdc.clockDedicatedRouteFalse(clkIO)
+  }
+})
--- a/fpga/src/main/scala/nexysvideo/Harness.scala
+++ b/fpga/src/main/scala/nexysvideo/Harness.scala
@@ -16,7 +16,6 @@ import sifive.blocks.devices.uart._

 import chipyard._
 import chipyard.harness._
-import chipyard.iobinders.{HasIOBinders}

 class NexysVideoHarness(override implicit val p: Parameters) extends NexysVideoShell {
  def dp = designParameters
--- a/fpga/src/main/scala/vc707/TestHarness.scala
+++ b/fpga/src/main/scala/vc707/TestHarness.scala
@@ -19,7 +19,6 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTPortIO}
 import sifive.blocks.devices.spi.{PeripherySPIKey, SPIPortIO}

 import chipyard._
-import chipyard.iobinders.{HasIOBinders}
 import chipyard.harness._

 class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707Shell { outer =>
--- a/fpga/src/main/scala/vcu118/TestHarness.scala
+++ b/fpga/src/main/scala/vcu118/TestHarness.scala
@@ -18,7 +18,6 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTPortIO}
 import sifive.blocks.devices.spi.{PeripherySPIKey, SPIPortIO}

 import chipyard._
-import chipyard.iobinders.{HasIOBinders}
 import chipyard.harness._

 class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118ShellBasicOverlays {
--- a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala
+++ b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala
@@ -13,7 +13,7 @@ import testchipip.{HasPeripheryTSIHostWidget, TSIHostWidgetIO}

 import chipyard.iobinders.{OverrideIOBinder, Port, TLMemPort}

-case class TSIHostWidgetPort(val io: TSIHostWidgetIO)
+case class TSIHostWidgetPort(val getIO: () => TSIHostWidgetIO)
  extends Port[TSIHostWidgetIO]

 class WithTSITLIOPassthrough extends OverrideIOBinder({
@@ -25,6 +25,6 @@ class WithTSITLIOPassthrough extends OverrideIOBinder({
    require(system.tsiSerial.size == 1)
    val io_tsi_serial_pins_temp = IO(DataMirror.internal.chiselTypeClone[TSIHostWidgetIO](system.tsiSerial.head)).suggestName("tsi_serial")
    io_tsi_serial_pins_temp <> system.tsiSerial.head
-    (Seq(TLMemPort(io_tsi_tl_mem_pins_temp), TSIHostWidgetPort(io_tsi_serial_pins_temp)), Nil)
+    (Seq(TLMemPort(() => io_tsi_tl_mem_pins_temp), TSIHostWidgetPort(() => io_tsi_serial_pins_temp)), Nil)
  }
 })
--- a/generators/caliptra-aes-acc
+++ b/generators/caliptra-aes-acc
--- a/generators/chipyard/src/main/scala/ChipTop.scala
+++ b/generators/chipyard/src/main/scala/ChipTop.scala
@@ -7,7 +7,7 @@ import scala.collection.mutable.{ArrayBuffer}
 import freechips.rocketchip.prci.{ClockGroupIdentityNode, ClockSinkParameters, ClockSinkNode, ClockGroup}
 import org.chipsalliance.cde.config.{Parameters, Field}
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyRawModuleImp, LazyModuleImpLike, BindingScope}
-import freechips.rocketchip.util.{ResetCatchAndSync}
+import freechips.rocketchip.util.{DontTouch}
 import chipyard.iobinders._

 import barstools.iocell.chisel._
@@ -30,5 +30,5 @@ class ChipTop(implicit p: Parameters) extends LazyModule with BindingScope
  // of ChipTop (ex: ClockGroup) do not receive clock or reset.
  // However. anonymous children of ChipTop should not need an implicit Clock or Reset
  // anyways, they probably need to be explicitly clocked.
-  lazy val module: LazyModuleImpLike = new LazyRawModuleImp(this) {  }
+  lazy val module: LazyModuleImpLike = new LazyRawModuleImp(this) with DontTouch {  }
 }
--- a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala
+++ b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala
@@ -65,11 +65,11 @@ class WithPLLSelectorDividerClockGenerator extends OverrideLazyIOBinder({
        o.reset := reset_wire
      }

-      (Seq(ClockPort(clock_io, 100), ResetPort(reset_io)), clockIOCell ++ resetIOCell)
+      (Seq(ClockPort(() => clock_io, 100), ResetPort(() => reset_io)), clockIOCell ++ resetIOCell)
    }
  }
 })
-
+ 
 // This passes all clocks through to the TestHarness
 class WithPassthroughClockGenerator extends OverrideLazyIOBinder({
  (system: HasChipyardPRCI) => {
@@ -92,9 +92,9 @@ class WithPassthroughClockGenerator extends OverrideLazyIOBinder({
        val clock_io = IO(Input(Clock())).suggestName(s"clock_${m.name.get}")
        b.clock := clock_io
        b.reset := reset_io
-        ClockPort(clock_io, freq)
+        ClockPort(() => clock_io, freq)
      }.toSeq
-      ((clock_ios :+ ResetPort(reset_io)), Nil)
+      ((clock_ios :+ ResetPort(() => reset_io)), Nil)
    }
  }
 })
--- a/generators/chipyard/src/main/scala/config/ChipConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala
@@ -43,6 +43,10 @@ class ChipLikeRocketConfig extends Config(

  new chipyard.config.AbstractConfig)

+class FlatChipTopChipLikeRocketConfig extends Config(
+  new chipyard.example.WithFlatChipTop ++
+  new chipyard.ChipLikeRocketConfig)
+
 // A simple config demonstrating a "bringup prototype" to bringup the ChipLikeRocketconfig
 class ChipBringupHostConfig extends Config(
  //=============================
--- a/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala
@@ -9,7 +9,7 @@ import freechips.rocketchip.diplomacy.{AsynchronousCrossing}

 // DOC include start: FFTRocketConfig
 class FFTRocketConfig extends Config(
-  new chipyard.iobinders.WithDontTouchIOBinders(false) ++              // TODO: hack around dontTouch not working in SFC
+  new chipyard.harness.WithDontTouchChipTopPorts(false) ++              // TODO: hack around dontTouch not working in SFC
  new fftgenerator.WithFFTGenerator(numPoints=8, width=16, decPt=8) ++ // add 8-point mmio fft at the default addr (0x2400) with 16bit fixed-point numbers.
  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
  new chipyard.config.AbstractConfig)
@@ -59,7 +59,7 @@ class LargeNVDLARocketConfig extends Config(
  new chipyard.config.AbstractConfig)

 class ManyMMIOAcceleratorRocketConfig extends Config(
-  new chipyard.iobinders.WithDontTouchIOBinders(false) ++   // TODO: hack around dontTouch not working in SFC
+  new chipyard.harness.WithDontTouchChipTopPorts(false) ++   // TODO: hack around dontTouch not working in SFC
  new fftgenerator.WithFFTGenerator(numPoints=8, width=16, decPt=8) ++ // add 8-point mmio fft at the default addr (0x2400) with 16bit fixed-point numbers.
  new chipyard.example.WithStreamingPassthrough ++          // use top with tilelink-controlled streaming passthrough
  new chipyard.example.WithStreamingFIR ++                  // use top with tilelink-controlled streaming FIR
--- a/generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala
@@ -0,0 +1,41 @@
+package chipyard
+
+import org.chipsalliance.cde.config.{Config}
+import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
+
+// ------------------------------------------------------------
+// Configs which demonstrate modifying the uncore memory system
+// ------------------------------------------------------------
+
+class SimAXIRocketConfig extends Config(
+  new chipyard.harness.WithSimAXIMem ++                     // drive the master AXI4 memory with a SimAXIMem, a 1-cycle magic memory, instead of default SimDRAM
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new chipyard.config.AbstractConfig)
+
+class GB1MemoryRocketConfig extends Config(
+  new freechips.rocketchip.subsystem.WithExtMemSize((1<<30) * 1L) ++ // use 1GB simulated external memory
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new chipyard.config.AbstractConfig)
+
+// DOC include start: mbusscratchpadrocket
+class MbusScratchpadOnlyRocketConfig extends Config(
+  new testchipip.WithMbusScratchpad(banks=2, partitions=2) ++ // add 2 partitions of 2 banks mbus backing scratchpad
+  new freechips.rocketchip.subsystem.WithNoMemPort ++         // remove offchip mem port
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new chipyard.config.AbstractConfig)
+// DOC include end: mbusscratchpadrocket
+
+class SbusScratchpadRocketConfig extends Config(
+  new testchipip.WithSbusScratchpad(base=0x70000000L, banks=4) ++ // add 4 banks sbus scratchpad
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new chipyard.config.AbstractConfig)
+
+class SbusBypassRocketConfig extends Config(
+  new freechips.rocketchip.subsystem.WithExtMemSbusBypass ++ // Add bypass path to access DRAM incoherently through an address alias
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new chipyard.config.AbstractConfig)
+
+class QuadChannelRocketConfig extends Config(
+  new freechips.rocketchip.subsystem.WithNMemoryChannels(4) ++      // 4 AXI4 channels
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new chipyard.config.AbstractConfig)
--- a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala
@@ -79,11 +79,6 @@ class ManyPeripheralsRocketConfig extends Config(
  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
  new chipyard.config.AbstractConfig)

-class QuadChannelRocketConfig extends Config(
-  new freechips.rocketchip.subsystem.WithNMemoryChannels(4) ++      // 4 AXI4 channels
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new chipyard.config.AbstractConfig)
-
 class UARTTSIRocketConfig extends Config(
  new chipyard.harness.WithSerialTLTiedOff ++
  new testchipip.WithUARTTSIClient ++
--- a/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala
@@ -56,3 +56,9 @@ class HwachaLargeBoomConfig extends Config(
  new boom.common.WithNLargeBooms(1) ++
  new chipyard.config.WithSystemBusWidth(128) ++
  new chipyard.config.AbstractConfig)
+
+class AES256ECBRocketConfig extends Config(
+  new aes.WithAES256ECBAccel ++                                   // use Caliptra AES 256 ECB accelerator
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new chipyard.config.WithSystemBusWidth(256) ++
+  new chipyard.config.AbstractConfig)
--- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
@@ -13,18 +13,13 @@ class RocketConfig extends Config(
  new chipyard.config.AbstractConfig)

 class TinyRocketConfig extends Config(
-  new chipyard.iobinders.WithDontTouchIOBinders(false) ++         // TODO FIX: Don't dontTouch the ports
+  new chipyard.harness.WithDontTouchChipTopPorts(false) ++         // TODO FIX: Don't dontTouch the ports
  new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++ // use incoherent bus topology
  new freechips.rocketchip.subsystem.WithNBanks(0) ++             // remove L2$
  new freechips.rocketchip.subsystem.WithNoMemPort ++             // remove backing memory
  new freechips.rocketchip.subsystem.With1TinyCore ++             // single tiny rocket-core
  new chipyard.config.AbstractConfig)

-class SimAXIRocketConfig extends Config(
-  new chipyard.harness.WithSimAXIMem ++                     // drive the master AXI4 memory with a SimAXIMem, a 1-cycle magic memory, instead of default SimDRAM
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new chipyard.config.AbstractConfig)
-
 class QuadRocketConfig extends Config(
  new freechips.rocketchip.subsystem.WithNBigCores(4) ++    // quad-core (4 RocketTiles)
  new chipyard.config.AbstractConfig)
@@ -39,11 +34,6 @@ class RV32RocketConfig extends Config(
  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
  new chipyard.config.AbstractConfig)

-class GB1MemoryRocketConfig extends Config(
-  new freechips.rocketchip.subsystem.WithExtMemSize((1<<30) * 1L) ++ // use 1GB simulated external memory
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new chipyard.config.AbstractConfig)
-
 // DOC include start: l1scratchpadrocket
 class ScratchpadOnlyRocketConfig extends Config(
  new chipyard.config.WithL2TLBs(0) ++
@@ -66,20 +56,6 @@ class L1ScratchpadRocketConfig extends Config(
  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
  new chipyard.config.AbstractConfig)

-// DOC include start: mbusscratchpadrocket
-class MbusScratchpadOnlyRocketConfig extends Config(
-  new testchipip.WithMbusScratchpad(banks=2, partitions=2) ++               // add 2 partitions of 2 banks mbus backing scratchpad
-  new freechips.rocketchip.subsystem.WithNoMemPort ++         // remove offchip mem port
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new chipyard.config.AbstractConfig)
-// DOC include end: mbusscratchpadrocket
-
-class SbusScratchpadRocketConfig extends Config(
-  new testchipip.WithSbusScratchpad(base=0x70000000L, banks=4) ++ // add 4 banks sbus backing scratchpad
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new chipyard.config.AbstractConfig)
-
-
 class MulticlockRocketConfig extends Config(
  new freechips.rocketchip.subsystem.WithAsynchronousRocketTiles(3, 3) ++ // Add async crossings between RocketTile and uncore
  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
@@ -98,6 +74,7 @@ class MulticlockRocketConfig extends Config(
  new chipyard.config.AbstractConfig)

 class CustomIOChipTopRocketConfig extends Config(
+  new chipyard.example.WithBrokenOutUARTIO ++
  new chipyard.example.WithCustomChipTop ++
  new chipyard.example.WithCustomIOCells ++
  new freechips.rocketchip.subsystem.WithNBigCores(1) ++         // single rocket-core
--- a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala
@@ -77,7 +77,7 @@ class TutorialSha3BlackBoxConfig extends Config(

 // Tutorial Phase 5: Map a multicore heterogeneous SoC with multiple cores and memory-mapped accelerators
 class TutorialNoCConfig extends Config(
-  new chipyard.iobinders.WithDontTouchIOBinders(false) ++
+  new chipyard.harness.WithDontTouchChipTopPorts(false) ++
  // Try changing the dimensions of the Mesh topology
  new constellation.soc.WithGlobalNoC(constellation.soc.GlobalNoCParams(
    NoCParams(
--- a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala
+++ b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala
@@ -13,6 +13,7 @@ import freechips.rocketchip.tilelink.{HasTLBusParams}

 import chipyard._
 import chipyard.clocking._
+import testchipip.{OffchipBusKey}

 // The default RocketChip BaseSubsystem drives its diplomatic clock graph
 // with the implicit clocks of Subsystem. Don't do that, instead we extend
@@ -103,6 +104,9 @@ class WithFrontBusFrequency(freqMHz: Double) extends Config((site, here, up) =>
 class WithControlBusFrequency(freqMHz: Double) extends Config((site, here, up) => {
  case ControlBusKey => up(ControlBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong)))
 })
+class WithOffchipBusFrequency(freqMHz: Double) extends Config((site, here, up) => {
+  case OffchipBusKey => up(OffchipBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).toLong)))
+})

 class WithRationalMemoryBusCrossing extends WithSbusToMbusCrossingType(RationalCrossing(Symmetric))
 class WithAsynchrousMemoryBusCrossing extends WithSbusToMbusCrossingType(AsynchronousCrossing())
--- a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala
+++ b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala
@@ -29,7 +29,7 @@ import chipyard.{ExtTLMem}
  * @param hang the power-on reset vector, i.e. the program counter will be set to this value on reset
  * @param contentFileName the path to the BootROM image
  */
-class WithBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt = 0x10040) extends Config((site, here, up) => {
+class WithBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt = 0x10000) extends Config((site, here, up) => {
  case BootROMLocated(x) => up(BootROMLocated(x), site)
      .map(_.copy(
        address = address,
--- a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala
+++ b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala
@@ -1,8 +1,9 @@
 package chipyard.config

 import org.chipsalliance.cde.config.{Config}
-import freechips.rocketchip.subsystem.{SystemBusKey, SubsystemBankedCoherenceKey, CoherenceManagerWrapper}
+import freechips.rocketchip.subsystem._
 import freechips.rocketchip.diplomacy.{DTSTimebase}
+import sifive.blocks.inclusivecache.{InclusiveCachePortParameters}

 // Replaces the L2 with a broadcast manager for maintaining coherence
 class WithBroadcastManager extends Config((site, here, up) => {
@@ -16,3 +17,13 @@ class WithSystemBusWidth(bitWidth: Int) extends Config((site, here, up) => {
 class WithDTSTimebase(freqMHz: BigInt) extends Config((site, here, up) => {
  case DTSTimebase => freqMHz
 })
+
+// Adds buffers on the interior of the inclusive LLC, to improve PD
+class WithInclusiveCacheInteriorBuffer(buffer: InclusiveCachePortParameters = InclusiveCachePortParameters.full) extends Config((site, here, up) => {
+  case InclusiveCacheKey => up(InclusiveCacheKey).copy(bufInnerInterior=buffer, bufOuterInterior=buffer)
+})
+
+// Adds buffers on the exterior of the inclusive LLC, to improve PD
+class WithInclusiveCacheExteriorBuffer(buffer: InclusiveCachePortParameters = InclusiveCachePortParameters.full) extends Config((site, here, up) => {
+  case InclusiveCacheKey => up(InclusiveCacheKey).copy(bufInnerExterior=buffer, bufOuterExterior=buffer)
+})
--- a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala
+++ b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala
@@ -66,6 +66,15 @@ class WithNPMPs(n: Int = 8) extends Config((site, here, up) => {
  }
 })

+class WithRocketCacheRowBits(rowBits: Int = 64) extends Config((site, here, up) => {
+  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem)) map {
+    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+      dcache = tp.tileParams.dcache.map(_.copy(rowBits = rowBits)),
+      icache = tp.tileParams.icache.map(_.copy(rowBits = rowBits))
+    ))
+  }
+})
+
 class WithRocketICacheScratchpad extends Config((site, here, up) => {
  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
@@ -96,3 +105,13 @@ class WithTilePrefetchers extends Config((site, here, up) => {
      master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
  }
 })
+
+// Adds boundary buffers to RocketTiles, which places buffers between the caches and the TileLink interface
+// This typically makes it easier to close timing
+class WithRocketBoundaryBuffers(buffers: Option[RocketTileBoundaryBufferParams] = Some(RocketTileBoundaryBufferParams(true))) extends Config((site, here, up) => {                                                                                                                                                           
+  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem)) map {                                                                                                                                                                                                                                                      
+    case tp: RocketTileAttachParams => tp.copy(tileParams=tp.tileParams.copy(                                                                                                                                                                                                                                                
+      boundaryBuffers=buffers                                                                                                                                                                                                                                                                                                
+    ))                                                                                                                                                                                                                                                                                                                       
+  }                                                                                                                                                                                                                                                                                                                          
+})   
--- a/generators/chipyard/src/main/scala/example/CustomChipTop.scala
+++ b/generators/chipyard/src/main/scala/example/CustomChipTop.scala
@@ -5,9 +5,11 @@ import chipyard.iobinders._

 import org.chipsalliance.cde.config._
 import freechips.rocketchip.diplomacy.{InModuleBody}
+import freechips.rocketchip.subsystem.{PBUS, HasTileLinkLocations}
 import barstools.iocell.chisel._
 import chipyard._
 import chipyard.harness.{BuildTop}
+import sifive.blocks.devices.uart._

 // A "custom" IOCell with additional I/O
 // The IO don't do anything here in this example
@@ -63,3 +65,21 @@ class WithCustomIOCells extends Config((site, here, up) => {
 class WithCustomChipTop extends Config((site, here, up) => {
  case BuildTop => (p: Parameters) => new CustomChipTop()(p)
 })
+
+class WithBrokenOutUARTIO extends OverrideIOBinder({
+  (system: HasPeripheryUARTModuleImp) => {
+    val uart_txd = IO(Output(Bool()))
+    val uart_rxd = IO(Input(Bool()))
+    system.uart(0).rxd := uart_rxd
+    uart_txd := system.uart(0).txd
+    val where = PBUS // TODO fix
+    val bus = system.outer.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(where)
+    val freqMHz = bus.dtsFrequency.get / 1000000
+    (Seq(UARTPort(() => {
+      val uart_wire = Wire(new UARTPortIO(system.uart(0).c))
+      uart_wire.txd := uart_txd
+      uart_rxd := uart_wire.rxd
+      uart_wire
+    }, 0, freqMHz.toInt)), Nil)
+  }
+})
--- a/generators/chipyard/src/main/scala/example/FlatChipTop.scala
+++ b/generators/chipyard/src/main/scala/example/FlatChipTop.scala
@@ -2,22 +2,28 @@ package chipyard.example


 import chisel3._
-import org.chipsalliance.cde.config.{Field, Parameters}
+import org.chipsalliance.cde.config.{Config, Field, Parameters}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.prci._
 import freechips.rocketchip.util._
+import freechips.rocketchip.subsystem.{PBUS, HasTileLinkLocations}
 import freechips.rocketchip.devices.debug.{ExportDebug, JtagDTMKey, Debug}
 import freechips.rocketchip.tilelink.{TLBuffer, TLFragmenter}
 import chipyard.{BuildSystem, DigitalTop}
+import chipyard.harness.{BuildTop}
 import chipyard.clocking._
-import chipyard.iobinders.{IOCellKey, JTAGChipIO}
+import chipyard.iobinders._
 import barstools.iocell.chisel._
+import testchipip.{SerialTLKey}

+class WithFlatChipTop extends Config((site, here, up) => {
+  case BuildTop => (p: Parameters) => new FlatChipTop()(p)
+})

 // This "FlatChipTop" uses no IOBinders, so all the IO have
 // to be explicitly constructed.
 // This only supports the base "DigitalTop"
-class FlatChipTop(implicit p: Parameters) extends LazyModule {
+class FlatChipTop(implicit p: Parameters) extends LazyModule with HasChipyardPorts {
  override lazy val desiredName = "ChipTop"
  val system = LazyModule(p(BuildSystem)(p)).suggestName("system").asInstanceOf[DigitalTop]

@@ -53,6 +59,8 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule {
  debugClockSinkNode := system.locateTLBusWrapper(p(ExportDebug).slaveWhere).fixedClockNode
  def debugClockBundle = debugClockSinkNode.in.head._1

+  var ports: Seq[Port[_]] = Nil
+
  override lazy val module = new FlatChipTopImpl
  class FlatChipTopImpl extends LazyRawModuleImp(this) {
    //=========================
@@ -68,6 +76,9 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule {
      o.reset := reset_wire
    }

+    ports = ports :+ ClockPort(() => clock_pad, 100.0)
+    ports = ports :+ ResetPort(() => reset_pad)
+
    // For a real chip you should replace this ClockSourceAtFreqFromPlusArg
    // with a blackbox of whatever PLL is being integrated
    val fake_pll = Module(new ClockSourceAtFreqFromPlusArg("pll_freq_mhz"))
@@ -83,11 +94,13 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule {
    // Custom Boot
    //=========================
    val (custom_boot_pad, customBootIOCell) = IOCell.generateIOFromSignal(system.custom_boot_pin.get.getWrappedValue, "custom_boot", p(IOCellKey))
+    ports = ports :+ CustomBootPort(() => custom_boot_pad)

    //=========================
    // Serialized TileLink
    //=========================
    val (serial_tl_pad, serialTLIOCells) = IOCell.generateIOFromSignal(system.serial_tl.get.getWrappedValue, "serial_tl", p(IOCellKey))
+    ports = ports :+ SerialTLPort(() => serial_tl_pad, p(SerialTLKey).get, system.serdesser.get, 0)

    //=========================
    // JTAG/Debug
@@ -126,12 +139,17 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule {
      IOCell.generateIOFromSignal(jtag_wire, "jtag", p(IOCellKey), abstractResetAsAsync = true)
    }.get

+    ports = ports :+ JTAGPort(() => jtag_pad)
+
    //==========================
    // UART
    //==========================
    require(system.uarts.size == 1)
    val (uart_pad, uartIOCells) = IOCell.generateIOFromSignal(system.module.uart.head, "uart_0", p(IOCellKey))
-
+    val where = PBUS // TODO fix
+    val bus = system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(where)
+    val freqMHz = bus.dtsFrequency.get / 1000000
+    ports = ports :+ UARTPort(() => uart_pad, 0, freqMHz.toInt)

    //==========================
    // External interrupts (tie off)
--- a/generators/chipyard/src/main/scala/example/GCD.scala
+++ b/generators/chipyard/src/main/scala/example/GCD.scala
@@ -13,7 +13,7 @@ import freechips.rocketchip.util.UIntIsOneOf

 // DOC include start: GCD params
 case class GCDParams(
-  address: BigInt = 0x1000,
+  address: BigInt = 0x4000,
  width: Int = 32,
  useAXI4: Boolean = false,
  useBlackBox: Boolean = true)
--- a/generators/chipyard/src/main/scala/harness/HarnessClocks.scala
+++ b/generators/chipyard/src/main/scala/harness/HarnessClocks.scala
@@ -10,7 +10,6 @@ import freechips.rocketchip.util.{ResetCatchAndSync}
 import freechips.rocketchip.prci._

 import chipyard.harness.{ApplyHarnessBinders, HarnessBinders, HarnessClockInstantiatorKey}
-import chipyard.iobinders.HasIOBinders
 import chipyard.clocking.{SimplePllConfiguration, ClockDividerN}


--- a/generators/chipyard/src/main/scala/harness/HasHarnessInstantiators.scala
+++ b/generators/chipyard/src/main/scala/harness/HasHarnessInstantiators.scala
@@ -5,12 +5,12 @@ import chisel3._
 import scala.collection.mutable.{ArrayBuffer, LinkedHashMap}
 import freechips.rocketchip.diplomacy.{LazyModule}
 import org.chipsalliance.cde.config.{Field, Parameters, Config}
-import freechips.rocketchip.util.{ResetCatchAndSync}
+import freechips.rocketchip.util.{ResetCatchAndSync, DontTouch}
 import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters, ClockSinkParameters, ClockParameters}
 import chipyard.stage.phases.TargetDirKey

 import chipyard.harness.{ApplyHarnessBinders, HarnessBinders}
-import chipyard.iobinders.HasIOBinders
+import chipyard.iobinders.HasChipyardPorts
 import chipyard.clocking.{SimplePllConfiguration, ClockDividerN}
 import chipyard.{ChipTop}

@@ -24,6 +24,7 @@ case object BuildTop extends Field[Parameters => LazyModule]((p: Parameters) =>
 case object HarnessClockInstantiatorKey extends Field[() => HarnessClockInstantiator]()
 case object HarnessBinderClockFrequencyKey extends Field[Double](100.0) // MHz
 case object MultiChipIdx extends Field[Int](0)
+case object DontTouchChipTopPorts extends Field[Boolean](true)

 class WithMultiChip(id: Int, p: Parameters) extends Config((site, here, up) => {
  case MultiChipParameters(`id`) => p
@@ -39,6 +40,10 @@ class WithHarnessBinderClockFreqMHz(freqMHz: Double) extends Config((site, here,
  case HarnessBinderClockFrequencyKey => freqMHz
 })

+class WithDontTouchChipTopPorts(b: Boolean = true) extends Config((site, here, up) => {
+  case DontTouchChipTopPorts => b
+})
+
 // A TestHarness mixing this in will
 // - use the HarnessClockInstantiator clock provide
 trait HasHarnessInstantiators {
@@ -83,12 +88,20 @@ trait HasHarnessInstantiators {

    withClockAndReset (harnessBinderClock, harnessBinderReset) {
      lazyDuts.zipWithIndex.foreach {
-        case (d: HasIOBinders, i: Int) => ApplyHarnessBinders(this, d.portMap.values.flatten.toSeq)(chipParameters(i))
+        case (d: HasChipyardPorts, i: Int) => {
+          ApplyHarnessBinders(this, d.ports)(chipParameters(i))
+        }
        case _ =>
      }
      ApplyMultiHarnessBinders(this, lazyDuts)
    }

+    if (p(DontTouchChipTopPorts)) {
+      duts.map(_ match {
+        case d: DontTouch => d.dontTouchPorts()
+      })
+    }
+
    val harnessBinderClk = harnessClockInstantiator.requestClockMHz("harnessbinder_clock", getHarnessBinderClockFreqMHz)
    println(s"Harness binder clock is $harnessBinderClockFreq")
    harnessBinderClock := harnessBinderClk
--- a/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala
+++ b/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala
@@ -13,7 +13,7 @@ import freechips.rocketchip.util._
 import testchipip._

 import chipyard._
-import chipyard.iobinders.{GetSystemParameters, JTAGChipIO, HasIOBinders, Port, SerialTLPort}
+import chipyard.iobinders.{GetSystemParameters, JTAGChipIO, HasChipyardPorts, Port, SerialTLPort}

 import scala.reflect.{ClassTag}

@@ -23,43 +23,43 @@ object ApplyMultiHarnessBinders {
  def apply(th: HasHarnessInstantiators, chips: Seq[LazyModule])(implicit p: Parameters): Unit = {
    Seq.tabulate(chips.size, chips.size) { case (i, j) => if (i != j) {
      (chips(i), chips(j)) match {
-        case (l0: HasIOBinders, l1: HasIOBinders) => p(MultiHarnessBinders(i, j)).foreach { f =>
-          f(l0.portMap.values.flatten.toSeq, l1.portMap.values.flatten.toSeq)
+        case (l0: HasChipyardPorts, l1: HasChipyardPorts) => p(MultiHarnessBinders(i, j)).foreach { f =>
+          f(th, l0.ports, l1.ports)
        }
      }
    }}
  }
 }

-class MultiHarnessBinder[T <: Port[_]](
+class MultiHarnessBinder[T <: Port[_], S <: HasHarnessInstantiators](
  chip0: Int, chip1: Int,
  chip0portFn: T => Boolean, chip1portFn: T => Boolean,
-  connectFn: (T, T) => Unit
-)(implicit tag: ClassTag[T]) extends Config((site, here, up) => {
+  connectFn: (S, T, T) => Unit
+)(implicit tag0: ClassTag[T], tag1: ClassTag[S]) extends Config((site, here, up) => {
    // Override any HarnessBinders for chip0/chip1
    case MultiChipParameters(`chip0`) => new Config(
-      new HarnessBinder({case (th, port: T) if chip0portFn(port) => }) ++ up(MultiChipParameters(chip0))
+      new HarnessBinder({case (th: S, port: T) if chip0portFn(port) => }) ++ up(MultiChipParameters(chip0))
    )
    case MultiChipParameters(`chip1`) => new Config(
-      new HarnessBinder({case (th, port: T) if chip1portFn(port) => }) ++ up(MultiChipParameters(chip1))
+      new HarnessBinder({case (th: S, port: T) if chip1portFn(port) => }) ++ up(MultiChipParameters(chip1))
    )
    // Set the multiharnessbinder key
    case MultiHarnessBinders(`chip0`, `chip1`) => up(MultiHarnessBinders(chip0, chip1)) :+ {
-      ((chip0Ports: Seq[Port[_]], chip1Ports: Seq[Port[_]]) => {
+      ((th: S, chip0Ports: Seq[Port[_]], chip1Ports: Seq[Port[_]]) => {
        val chip0Port: Seq[T] = chip0Ports.collect { case (p: T) if chip0portFn(p) => p }
        val chip1Port: Seq[T] = chip1Ports.collect { case (p: T) if chip1portFn(p) => p }
        require(chip0Port.size == 1 && chip1Port.size == 1)
-        connectFn(chip0Port(0), chip1Port(0))
+        connectFn(th, chip0Port(0), chip1Port(0))
      })
    }
  })


-class WithMultiChipSerialTL(chip0: Int, chip1: Int, chip0portId: Int = 0, chip1portId: Int = 0) extends MultiHarnessBinder[SerialTLPort](
+class WithMultiChipSerialTL(chip0: Int, chip1: Int, chip0portId: Int = 0, chip1portId: Int = 0) extends MultiHarnessBinder(
  chip0, chip1,
  (p0: SerialTLPort) => p0.portId == chip0portId,
  (p1: SerialTLPort) => p1.portId == chip1portId,
-  (p0: SerialTLPort, p1: SerialTLPort) => {
+  (th: HasHarnessInstantiators, p0: SerialTLPort, p1: SerialTLPort) => {
    (DataMirror.directionOf(p0.io.clock), DataMirror.directionOf(p1.io.clock)) match {
      case (Direction.Input, Direction.Output) => p0.io.clock := p1.io.clock
      case (Direction.Output, Direction.Input) => p1.io.clock := p0.io.clock
--- a/generators/chipyard/src/main/scala/harness/TestHarness.scala
+++ b/generators/chipyard/src/main/scala/harness/TestHarness.scala
@@ -9,7 +9,6 @@ import freechips.rocketchip.util.{ResetCatchAndSync}
 import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters, ClockSinkParameters, ClockParameters}

 import chipyard.harness.{ApplyHarnessBinders, HarnessBinders}
-import chipyard.iobinders.HasIOBinders
 import chipyard.clocking.{SimplePllConfiguration, ClockDividerN}
 import chipyard.{ChipTop}

--- a/generators/chipyard/src/main/scala/harness/package.scala
+++ b/generators/chipyard/src/main/scala/harness/package.scala
@@ -7,5 +7,5 @@ package object harness
 {
  import chipyard.iobinders.Port
  type HarnessBinderFunction = PartialFunction[(HasHarnessInstantiators, Port[_]), Unit]
-  type MultiHarnessBinderFunction = (Seq[Port[_]], Seq[Port[_]]) => Unit
+  type MultiHarnessBinderFunction = (HasHarnessInstantiators, Seq[Port[_]], Seq[Port[_]]) => Unit
 }
--- a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala
+++ b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala
@@ -51,13 +51,7 @@ case object IOBinders extends Field[Map[String, Seq[IOBinderFunction]]](
  Map[String, Seq[IOBinderFunction]]().withDefaultValue(Nil)
 )

-case object DontTouchIOBindersPorts extends Field[Boolean](true)
-
-class WithDontTouchIOBinders(b: Boolean = true) extends Config((site, here, up) => {
-  case DontTouchIOBindersPorts => b
-})
-
-abstract trait HasIOBinders { this: LazyModule =>
+abstract trait HasIOBinders extends HasChipyardPorts { this: LazyModule =>
  val lazySystem: LazyModule
  private val iobinders = p(IOBinders)
  // Note: IOBinders cannot rely on the implicit clock/reset, as they may be called from the
@@ -81,11 +75,9 @@ abstract trait HasIOBinders { this: LazyModule =>
  // A mapping between stringified DigitalSystem traits and their corresponding ChipTop iocells
  val iocellMap = InModuleBody { iobinders.keys.map(k => k -> (lzyFlattened(k)._2 ++ impFlattened(k)._2)).toMap }

-  InModuleBody {
-    if (p(DontTouchIOBindersPorts)) {
-      portMap.values.flatten.foreach { case (port: Port[Data]) => dontTouch(port.io) }
-    }
+  def ports = portMap.getWrappedValue.values.flatten.toSeq

+  InModuleBody {
    println("IOCells generated by IOBinders:")
    for ((k, v) <- iocellMap) {
      if (!v.isEmpty) {
@@ -172,7 +164,7 @@ class WithGPIOCells extends OverrideIOBinder({
        iocell.io.ie := pin.o.ie
        pin.i.ival := iocell.io.i
        iocell.io.pad <> g
-        (GPIOPort(g, i, j), iocell)
+        (GPIOPort(() => g, i, j), iocell)
      }).unzip
    }).unzip
    (ports2d.flatten, cells2d.flatten)
@@ -184,7 +176,7 @@ class WithGPIOPunchthrough extends OverrideIOBinder({
    val ports = system.gpio.zipWithIndex.map { case (gpio, i) =>
      val io_gpio = IO(gpio.cloneType).suggestName(s"gpio_$i")
      io_gpio <> gpio
-      GPIOPinsPort(io_gpio, i)
+      GPIOPinsPort(() => io_gpio, i)
    }
    (ports, Nil)
  }
@@ -195,7 +187,7 @@ class WithI2CPunchthrough extends OverrideIOBinder({
    val ports = system.i2c.zipWithIndex.map { case (i2c, i) =>
      val io_i2c = IO(i2c.cloneType).suggestName(s"i2c_$i")
      io_i2c <> i2c
-      I2CPort(i2c)
+      I2CPort(() => i2c)
    }
    (ports, Nil)
  }
@@ -209,7 +201,7 @@ class WithUARTIOCells extends OverrideIOBinder({
      val where = PBUS // TODO fix
      val bus = system.outer.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(where)
      val freqMHz = bus.dtsFrequency.get / 1000000
-      (UARTPort(port, i, freqMHz.toInt), ios)
+      (UARTPort(() => port, i, freqMHz.toInt), ios)
    }).unzip
    (ports, cells2d.flatten)
  }
@@ -227,7 +219,7 @@ class WithSPIIOPunchthrough extends OverrideLazyIOBinder({
      val ports = spi.zipWithIndex.map({ case (s, i) =>
        val io_spi = IO(s.cloneType).suggestName(s"spi_$i")
        io_spi <> s
-        SPIPort(io_spi)
+        SPIPort(() => io_spi)
      })
      (ports, Nil)
    }
@@ -257,7 +249,7 @@ class WithSPIFlashIOCells extends OverrideIOBinder({
        iocell
      }

-      (SPIFlashPort(port, system.p(PeripherySPIFlashKey)(i), i), dqIOs ++ csIOs ++ sckIOs)
+      (SPIFlashPort(() => port, system.p(PeripherySPIFlashKey)(i), i), dqIOs ++ csIOs ++ sckIOs)
    }).unzip
    (ports, cells2d.flatten)
  }
@@ -267,7 +259,7 @@ class WithExtInterruptIOCells extends OverrideIOBinder({
  (system: HasExtInterruptsModuleImp) => {
    if (system.outer.nExtInterrupts > 0) {
      val (port: UInt, cells) = IOCell.generateIOFromSignal(system.interrupts, "ext_interrupts", system.p(IOCellKey), abstractResetAsAsync = true)
-      (Seq(ExtIntPort(port)), cells)
+      (Seq(ExtIntPort(() => port)), cells)
    } else {
      system.interrupts := DontCare // why do I have to drive this 0-wide wire???
      (Nil, Nil)
@@ -318,7 +310,7 @@ class WithDebugIOCells extends OverrideLazyIOBinder({
        // Add IOCells for the DMI/JTAG/APB ports
        val dmiTuple = debug.clockeddmi.map { d =>
          val (port, cells) = IOCell.generateIOFromSignal(d, "dmi", p(IOCellKey), abstractResetAsAsync = true)
-          (DMIPort(port), cells)
+          (DMIPort(() => port), cells)
        }

        val jtagTuple = debug.systemjtag.map { j =>
@@ -328,7 +320,7 @@ class WithDebugIOCells extends OverrideLazyIOBinder({
          j.jtag.TDI := jtag_wire.TDI
          jtag_wire.TDO := j.jtag.TDO.data
          val (port, cells) = IOCell.generateIOFromSignal(jtag_wire, "jtag", p(IOCellKey), abstractResetAsAsync = true)
-          (JTAGPort(port), cells)
+          (JTAGPort(() => port), cells)
        }

        require(!debug.apb.isDefined)
@@ -345,7 +337,7 @@ class WithSerialTLIOCells extends OverrideIOBinder({
    val (ports, cells) = system.serial_tl.zipWithIndex.map({ case (s, id) =>
      val sys = system.asInstanceOf[BaseSubsystem]
      val (port, cells) = IOCell.generateIOFromSignal(s.getWrappedValue, "serial_tl", sys.p(IOCellKey), abstractResetAsAsync = true)
-      (SerialTLPort(port, sys.p(SerialTLKey).get, system.serdesser.get, id), cells)
+      (SerialTLPort(() => port, sys.p(SerialTLKey).get, system.serdesser.get, id), cells)
    }).unzip
    (ports.toSeq, cells.flatten.toSeq)
  }
@@ -355,9 +347,9 @@ class WithSerialTLPunchthrough extends OverrideIOBinder({
  (system: CanHavePeripheryTLSerial) => {
    val (ports, cells) = system.serial_tl.zipWithIndex.map({ case (s, id) =>
      val sys = system.asInstanceOf[BaseSubsystem]
-      val port = IO(s.getWrappedValue.cloneType)
+      val port = IO(chiselTypeOf(s.getWrappedValue))
      port <> s.getWrappedValue
-      (SerialTLPort(port, sys.p(SerialTLKey).get, system.serdesser.get, id), Nil)
+      (SerialTLPort(() => port, sys.p(SerialTLKey).get, system.serdesser.get, id), Nil)
    }).unzip
    (ports.toSeq, cells.flatten.toSeq)
  }
@@ -375,7 +367,7 @@ class WithAXI4MemPunchthrough extends OverrideLazyIOBinder({
        val port = IO(new ClockedIO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m))).suggestName(s"axi4_mem_${i}")
        port.bits <> m
        port.clock := clockBundle.clock
-        AXI4MemPort(port, p(ExtMem).get, system.memAXI4Node.edges.in(i), p(MemoryBusKey).dtsFrequency.get.toInt)
+        AXI4MemPort(() => port, p(ExtMem).get, system.memAXI4Node.edges.in(i), p(MemoryBusKey).dtsFrequency.get.toInt)
      }).toSeq
      (ports, Nil)
    }
@@ -394,7 +386,7 @@ class WithAXI4MMIOPunchthrough extends OverrideLazyIOBinder({
        val port = IO(new ClockedIO(DataMirror.internal.chiselTypeClone[AXI4Bundle](m))).suggestName(s"axi4_mmio_${i}")
        port.bits <> m
        port.clock := clockBundle.clock
-        AXI4MMIOPort(port, p(ExtBus).get, system.mmioAXI4Node.edges.in(i))
+        AXI4MMIOPort(() => port, p(ExtBus).get, system.mmioAXI4Node.edges.in(i))
      }).toSeq
      (ports, Nil)
    }
@@ -413,7 +405,7 @@ class WithL2FBusAXI4Punchthrough extends OverrideLazyIOBinder({
        val port = IO(new ClockedIO(Flipped(DataMirror.internal.chiselTypeClone[AXI4Bundle](m)))).suggestName(s"axi4_fbus_${i}")
        m <> port.bits
        port.clock := clockBundle.clock
-        AXI4InPort(port, p(ExtIn).get)
+        AXI4InPort(() => port, p(ExtIn).get)
      }).toSeq
      (ports, Nil)
    }
@@ -427,7 +419,7 @@ class WithBlockDeviceIOPunchthrough extends OverrideIOBinder({
      val bdParams = p(BlockDeviceKey).get
      val port = IO(new ClockedIO(new BlockDeviceIO(bdParams))).suggestName("blockdev")
      port <> bdev
-      BlockDevicePort(port, bdParams)
+      BlockDevicePort(() => port, bdParams)
    }).toSeq
    (ports, Nil)
  }
@@ -439,7 +431,7 @@ class WithNICIOPunchthrough extends OverrideIOBinder({
      val p = GetSystemParameters(system)
      val port = IO(new ClockedIO(new NICIOvonly)).suggestName("nic")
      port <> n
-      NICPort(port, p(NICKey).get)
+      NICPort(() => port, p(NICKey).get)
    }).toSeq
    (ports, Nil)
  }
@@ -449,7 +441,7 @@ class WithTraceGenSuccessPunchthrough extends OverrideIOBinder({
  (system: TraceGenSystemModuleImp) => {
    val success: Bool = IO(Output(Bool())).suggestName("success")
    success := system.success
-    (Seq(SuccessPort(success)), Nil)
+    (Seq(SuccessPort(() => success)), Nil)
  }
 })

@@ -472,7 +464,7 @@ class WithTraceIOPunchthrough extends OverrideLazyIOBinder({
        bootrom = chipyardSystem.bootROM.map(_.module.contents.toArray.mkString(" ")).getOrElse(""),
        has_dtm = p(ExportDebug).protocols.contains(DMI) // assume that exposing clockeddmi means we will connect SimDTM
      )
-      TracePort(trace, cfg)
+      TracePort(() => trace, cfg)
    }
    (ports.toSeq, Nil)
  }
@@ -482,7 +474,7 @@ class WithCustomBootPin extends OverrideIOBinder({
  (system: CanHavePeripheryCustomBootPin) => system.custom_boot_pin.map({ p =>
    val sys = system.asInstanceOf[BaseSubsystem]
    val (port, cells) = IOCell.generateIOFromSignal(p.getWrappedValue, "custom_boot", sys.p(IOCellKey), abstractResetAsAsync = true)
-    (Seq(CustomBootPort(port)), cells)
+    (Seq(CustomBootPort(() => port)), cells)
  }).getOrElse((Nil, Nil))
 })

@@ -491,7 +483,7 @@ class WithUARTTSIPunchthrough extends OverrideIOBinder({
    val sys = system.asInstanceOf[BaseSubsystem]
    val uart_tsi = IO(new UARTTSIIO(p.uartParams))
    uart_tsi <> p
-    (Seq(UARTTSIPort(uart_tsi)), Nil)
+    (Seq(UARTTSIPort(() => uart_tsi)), Nil)
  }).getOrElse((Nil, Nil))
 })

@@ -499,7 +491,7 @@ class WithTLMemPunchthrough extends OverrideIOBinder({
  (system: CanHaveMasterTLMemPort) => {
    val io_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](system.mem_tl)).suggestName("tl_slave")
    io_tl_mem_pins_temp <> system.mem_tl
-    (Seq(TLMemPort(io_tl_mem_pins_temp)), Nil)
+    (Seq(TLMemPort(() => io_tl_mem_pins_temp)), Nil)
  }
 })

--- a/generators/chipyard/src/main/scala/iobinders/Ports.scala
+++ b/generators/chipyard/src/main/scala/iobinders/Ports.scala
@@ -16,79 +16,85 @@ import freechips.rocketchip.util.{HeterogeneousBag}
 import freechips.rocketchip.tilelink.{TLBundle}

 trait Port[T <: Data] {
-  val io: T
+  val getIO: () => T
+  // port.io should only be called in the TestHarness context
+  lazy val io = getIO()
+}
+
+trait HasChipyardPorts {
+  def ports: Seq[Port[_]]
 }

 // These case classes are generated by IOBinders, and interpreted by HarnessBinders
-case class GPIOPort        (val io: Analog, val gpioId: Int, val pinId: Int)
+case class GPIOPort        (val getIO: () => Analog, val gpioId: Int, val pinId: Int)
    extends Port[Analog]

-case class GPIOPinsPort    (val io: GPIOPortIO, val gpioId: Int)
+case class GPIOPinsPort    (val getIO: () => GPIOPortIO, val gpioId: Int)
    extends Port[GPIOPortIO]

-case class I2CPort         (val io: sifive.blocks.devices.i2c.I2CPort)
+case class I2CPort         (val getIO: () => sifive.blocks.devices.i2c.I2CPort)
    extends Port[sifive.blocks.devices.i2c.I2CPort]

-case class UARTPort        (val io: UARTPortIO, val uartNo: Int, val freqMHz: Int)
+case class UARTPort        (val getIO: () => UARTPortIO, val uartNo: Int, val freqMHz: Int)
    extends Port[UARTPortIO]

-case class SPIFlashPort    (val io: SPIChipIO, val params: SPIFlashParams, val spiId: Int)
+case class SPIFlashPort    (val getIO: () => SPIChipIO, val params: SPIFlashParams, val spiId: Int)
    extends Port[SPIChipIO]

-case class SPIPort         (val io: SPIPortIO)
+case class SPIPort         (val getIO: () => SPIPortIO)
    extends Port[SPIPortIO]

-case class BlockDevicePort (val io: ClockedIO[BlockDeviceIO], val params: BlockDeviceConfig)
+case class BlockDevicePort (val getIO: () => ClockedIO[BlockDeviceIO], val params: BlockDeviceConfig)
    extends Port[ClockedIO[BlockDeviceIO]]

-case class NICPort         (val io: ClockedIO[NICIOvonly], val params: NICConfig)
+case class NICPort         (val getIO: () => ClockedIO[NICIOvonly], val params: NICConfig)
    extends Port[ClockedIO[NICIOvonly]]

-case class AXI4MemPort     (val io: ClockedIO[AXI4Bundle], val params: MemoryPortParams, val edge: AXI4EdgeParameters, val clockFreqMHz: Int)
+case class AXI4MemPort     (val getIO: () => ClockedIO[AXI4Bundle], val params: MemoryPortParams, val edge: AXI4EdgeParameters, val clockFreqMHz: Int)
    extends Port[ClockedIO[AXI4Bundle]]

-case class AXI4MMIOPort    (val io: ClockedIO[AXI4Bundle], val params: MasterPortParams, val edge: AXI4EdgeParameters)
+case class AXI4MMIOPort    (val getIO: () => ClockedIO[AXI4Bundle], val params: MasterPortParams, val edge: AXI4EdgeParameters)
    extends Port[ClockedIO[AXI4Bundle]]

-case class AXI4InPort      (val io: ClockedIO[AXI4Bundle], val params: SlavePortParams)
+case class AXI4InPort      (val getIO: () => ClockedIO[AXI4Bundle], val params: SlavePortParams)
    extends Port[ClockedIO[AXI4Bundle]]

-case class ExtIntPort      (val io: UInt)
+case class ExtIntPort      (val getIO: () => UInt)
    extends Port[UInt]

-case class DMIPort         (val io: ClockedDMIIO)
+case class DMIPort         (val getIO: () => ClockedDMIIO)
    extends Port[ClockedDMIIO]

-case class JTAGPort        (val io: JTAGChipIO)
+case class JTAGPort        (val getIO: () => JTAGChipIO)
    extends Port[JTAGChipIO]

-case class SerialTLPort    (val io: ClockedIO[SerialIO], val params: SerialTLParams, val serdesser: TLSerdesser, val portId: Int)
+case class SerialTLPort    (val getIO: () => ClockedIO[SerialIO], val params: SerialTLParams, val serdesser: TLSerdesser, val portId: Int)
    extends Port[ClockedIO[SerialIO]]

-case class UARTTSIPort     (val io: UARTTSIIO)
+case class UARTTSIPort     (val getIO: () => UARTTSIIO)
    extends Port[UARTTSIIO]

-case class SuccessPort     (val io: Bool)
+case class SuccessPort     (val getIO: () => Bool)
    extends Port[Bool]

-case class TracePort       (val io: TraceOutputTop, val cosimCfg: SpikeCosimConfig)
+case class TracePort       (val getIO: () => TraceOutputTop, val cosimCfg: SpikeCosimConfig)
    extends Port[TraceOutputTop]

-case class CustomBootPort  (val io: Bool)
+case class CustomBootPort  (val getIO: () => Bool)
    extends Port[Bool]

-case class ClockPort       (val io: Clock, val freqMHz: Double)
+case class ClockPort       (val getIO: () => Clock, val freqMHz: Double)
    extends Port[Clock]

-case class ResetPort       (val io: AsyncReset)
+case class ResetPort       (val getIO: () => AsyncReset)
    extends Port[Reset]

-case class DebugResetPort  (val io: Reset)
+case class DebugResetPort  (val getIO: () => Reset)
    extends Port[Reset]

-case class JTAGResetPort   (val io: Reset)
+case class JTAGResetPort   (val getIO: () => Reset)
    extends Port[Reset]

-case class TLMemPort       (val io: HeterogeneousBag[TLBundle])
+case class TLMemPort       (val getIO: () => HeterogeneousBag[TLBundle])
    extends Port[HeterogeneousBag[TLBundle]]

--- a/generators/firechip/src/main/scala/TargetConfigs.scala
+++ b/generators/firechip/src/main/scala/TargetConfigs.scala
@@ -106,7 +106,7 @@ class WithFireSimDesignTweaks extends Config(
  new chipyard.config.WithUARTInitBaudRate(BigInt(3686400L)) ++
  // Optional: Adds IO to attach tracerV bridges
  new chipyard.config.WithTraceIO ++
-  // Optional: Request 16 GiB of target-DRAM by default (can safely request up to 32 GiB on F1)
+  // Optional: Request 16 GiB of target-DRAM by default (can safely request up to 64 GiB on F1)
  new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 16L) ++
  // Optional: Removing this will require using an initramfs under linux
  new testchipip.WithBlockDevice
--- a/generators/rocc-acc-utils
+++ b/generators/rocc-acc-utils
--- a/generators/rocket-chip
+++ b/generators/rocket-chip
--- a/generators/testchipip
+++ b/generators/testchipip
--- a/scripts/build-setup.sh
+++ b/scripts/build-setup.sh
@@ -148,10 +148,40 @@ if run_step "1"; then

    # use conda-lock to create env
    conda-lock install --conda $(which conda) -p $CYDIR/.conda-env $LOCKFILE &&
-
    source $CYDIR/.conda-env/etc/profile.d/conda.sh &&
    conda activate $CYDIR/.conda-env
    exit_if_last_command_failed
+
+    # install circt into conda
+    git submodule update --init $CYDIR/tools/install-circt &&
+    $CYDIR/tools/install-circt/bin/download-release-or-nightly-circt.sh \
+        -f circt-full-shared-linux-x64.tar.gz \
+        -i $CONDA_PREFIX \
+        -v version-file \
+        -x $CYDIR/conda-reqs/circt.json \
+        -g null
+    exit_if_last_command_failed
+
+    # Conda Setup
+    # Provide a sourceable snippet that can be used in subshells that may not have
+    # inhereted conda functions that would be brought in under a login shell that
+    # has run conda init (e.g., VSCode, CI)
+    read -r -d '\0' CONDA_ACTIVATE_PREAMBLE <<'END_CONDA_ACTIVATE'
+if ! type conda >& /dev/null; then
+    echo "::ERROR:: you must have conda in your environment first"
+    return 1  # don't want to exit here because this file is sourced
+fi
+
+# if we're sourcing this in a sub process that has conda in the PATH but not as a function, init it again
+conda activate --help >& /dev/null || source $(conda info --base)/etc/profile.d/conda.sh
+\0
+END_CONDA_ACTIVATE
+
+    replace_content env.sh build-setup-conda "# line auto-generated by $0
+$CONDA_ACTIVATE_PREAMBLE
+conda activate $CYDIR/.conda-env
+source $CYDIR/scripts/fix-open-files.sh"
+
 fi

 if [ -z "$FORCE_FLAG" ]; then
@@ -250,12 +280,6 @@ if run_step "10"; then
    exit_if_last_command_failed
 fi

-cat <<EOT >> env.sh
-# line auto-generated by $0
-conda activate $CYDIR/.conda-env
-source $CYDIR/scripts/fix-open-files.sh
-EOT
-
 echo "Setup complete!"

 } 2>&1 | tee build-setup.log
--- a/scripts/build-toolchain-extra.sh
+++ b/scripts/build-toolchain-extra.sh
@@ -118,4 +118,11 @@ cd tools/DRAMSim2
 make libdramsim.so
 cp libdramsim.so $RISCV/lib/

+echo '==>  Installing uart_tsi bringup utility'
+cd $RDIR
+git submodule update --init generators/testchipip
+cd generators/testchipip/uart_tsi
+make
+cp uart_tsi $RISCV/bin
+
 echo "Extra Toolchain Utilities/Tests Build Complete!"
--- a/scripts/generate-conda-lockfiles.sh
+++ b/scripts/generate-conda-lockfiles.sh
@@ -13,6 +13,13 @@ fi
 for TOOLCHAIN_TYPE in riscv-tools esp-tools; do
    # note: lock file must end in .conda-lock.yml - see https://github.com/conda-incubator/conda-lock/issues/154
    LOCKFILE=$REQS_DIR/conda-lock-reqs/conda-requirements-$TOOLCHAIN_TYPE-linux-64.conda-lock.yml
+    rm -rf $LOCKFILE

-    conda-lock -f "$REQS_DIR/chipyard.yaml" -f "$REQS_DIR/$TOOLCHAIN_TYPE.yaml" -p linux-64 --lockfile $LOCKFILE
+    conda-lock \
+	    --no-mamba \
+	    --no-micromamba \
+	    -f "$REQS_DIR/chipyard.yaml" \
+	    -f "$REQS_DIR/$TOOLCHAIN_TYPE.yaml" \
+	    -p linux-64 \
+	    --lockfile $LOCKFILE
 done
--- a/scripts/init-submodules-no-riscv-tools-nolog.sh
+++ b/scripts/init-submodules-no-riscv-tools-nolog.sh
@@ -157,8 +157,6 @@ if [ ! -f ./software/firemarshal/marshal-config.yaml ]; then
  echo "firesim-dir: '../../sims/firesim/'" > ./software/firemarshal/marshal-config.yaml
 fi

-cat << EOT >> env.sh
-# line auto-generated by init-submodules-no-riscv-tools.sh
+replace_content env.sh init-submodules "# line auto-generated by init-submodules-no-riscv-tools.sh
 __DIR="$RDIR"
-PATH=\$__DIR/software/firemarshal:\$PATH
-EOT
+PATH=\$__DIR/software/firemarshal:\$PATH"
--- a/scripts/insert-includes.py
+++ b/scripts/insert-includes.py
@@ -1,6 +1,7 @@
 #!/usr/bin/env python

-# replaces a `include with the full include file
+# replaces a `include with the full include file.
+# recursively replaces `include's until none are left
 #
 # args
 # $1 - file to remove includes from
@@ -12,6 +13,8 @@
 import sys
 import re
 import os
+import tempfile
+import shutil

 inVlog = sys.argv[1]
 outVlog = sys.argv[2]
@@ -24,28 +27,52 @@ if inVlog == outVlog:
 incDirs = sys.argv[3:]
 print("[INFO] Searching following dirs for includes: " + str(incDirs))

-# open file
-with open(inVlog, 'r') as inFile:
-    with open(outVlog, 'w') as outFile:
-        # for each include found, search through all dirs and replace if found, error if not
-        for num, line in enumerate(inFile, 1):
+def process(inF, outF):
+    # open file
+    with open(inF, 'r') as inFile:
+        with open(outF, 'w') as outFile:
+            # for each include found, search through all dirs and replace if found, error if not
+            for num, line in enumerate(inFile, 1):
+                match = re.match(r"^ *`include +\"(.*)\"", line)
+                if match:
+                    # search for include and replace
+                    found = False
+                    for d in incDirs:
+                        potentialIncFileName = d + "/" + match.group(1)
+                        if os.path.exists(potentialIncFileName):
+                            found = True
+                            with open(potentialIncFileName, 'r') as incFile:
+                                for iline in incFile:
+                                    outFile.write(iline)
+                            break
+
+                    # must find something to include with
+                    if not found:
+                        sys.exit("[ERROR] Couldn't replace include \"" + str(match.group(1)) + "\" found on line " + str(num))
+                else:
+                    outFile.write(line)
+
+inF = inVlog
+
+while True:
+    # create a copy of the input
+    fd, temp_path = tempfile.mkstemp()
+    shutil.copy2(inF, temp_path)
+
+    with open(temp_path, 'r') as inFile:
+        anyIncludes = False
+        for line in inFile:
            match = re.match(r"^ *`include +\"(.*)\"", line)
            if match:
-                # search for include and replace
-                found = False
-                for d in incDirs:
-                    potentialIncFileName = d + "/" + match.group(1)
-                    if os.path.exists(potentialIncFileName):
-                        found = True
-                        with open(potentialIncFileName, 'r') as incFile:
-                            for iline in incFile:
-                                outFile.write(iline)
-                        break
+                anyIncludes = True
+                break

-                # must find something to include with
-                if not found:
-                    sys.exit("[ERROR] Couldn't replace include \"" + str(match.group(1)) + "\" found on line " + str(num))
-            else:
-                outFile.write(line)
+        if anyIncludes:
+            process(temp_path, outVlog)
+            inF = outVlog
+            os.remove(temp_path)
+        else:
+            os.remove(temp_path)
+            break

 print("[INFO] Success. Writing output to: " + str(outVlog))
--- a/scripts/replace-content.py
+++ b/scripts/replace-content.py
@@ -0,0 +1,56 @@
+#!/usr/bin/env python
+
+# Replace text in a file given a key identifying a block to replace.
+# If the file doesn't exist, create it.
+#
+# args
+# $1 - file to replace text in
+# $2 - key used to find block of text to replace
+# $3 - text to fill in block that is replaced
+
+import re
+import sys
+
+def CY_INITIALIZE_RE_BLOCK(k):
+    return (
+        r"^# >>> " + f"{k}" + r" initialize >>>(?:\n|\r\n)"
+        r"([\s\S]*?)"
+        r"# <<< " + f"{k}" + r" initialize <<<(?:\n|\r\n)?"
+    )
+
+def CY_INITIALIZE_START_TOKEN(k):
+    return "# >>> " + f"{k}" + " initialize >>>"
+
+def CY_INITIALIZE_END_TOKEN(k):
+    return "# <<< " + f"{k}" + " initialize <<<"
+
+# ------------------------------
+
+try:
+    with open(sys.argv[1]) as fh:
+        fh_content = fh.read()
+except FileNotFoundError:
+    fh_content = ""
+except:
+    raise
+
+initialize_comment_key = sys.argv[2]
+inner_contents = CY_INITIALIZE_START_TOKEN(initialize_comment_key) + "\n" + sys.argv[3] + "\n" + CY_INITIALIZE_END_TOKEN(initialize_comment_key) + "\n"
+
+# ------------------------------
+
+replace_str = "__CY_REPLACE_ME_123__"
+fh_content = re.sub(
+    CY_INITIALIZE_RE_BLOCK(initialize_comment_key),
+    replace_str,
+    fh_content,
+    flags=re.MULTILINE,
+)
+# TODO: maybe remove all but last of replace_str, if there's more than one occurrence
+fh_content = fh_content.replace(replace_str, inner_contents)
+
+if CY_INITIALIZE_START_TOKEN(initialize_comment_key) not in fh_content:
+    fh_content += "\n%s\n" % inner_contents
+
+with open(sys.argv[1], "w") as fh:
+    fh.write(fh_content)
--- a/scripts/tutorial-patches/build.sbt.patch
+++ b/scripts/tutorial-patches/build.sbt.patch
@@ -1,20 +1,20 @@
 diff --git a/build.sbt b/build.sbt
-index 302d99e6..0aa0fcb4 100644
+index c3be6161..2a6d7160 100644
 --- a/build.sbt
 +++ b/build.sbt
-@@ -148,7 +148,7 @@ lazy val testchipip = (project in file("generators/testchipip"))
-
+@@ -147,7 +147,7 @@ lazy val testchipip = (project in file("generators/testchipip"))
+ 
 lazy val chipyard = (project in file("generators/chipyard"))
   .dependsOn(testchipip, rocketchip, boom, hwacha, sifive_blocks, sifive_cache, iocell,
 -    sha3, // On separate line to allow for cleaner tutorial-setup patches
 +    //sha3, // On separate line to allow for cleaner tutorial-setup patches
     dsptools, rocket_dsp_utils,
     gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
-     constellation, mempress, barf, shuttle)
-@@ -220,10 +220,10 @@ lazy val sodor = (project in file("generators/riscv-sodor"))
+     constellation, mempress, barf, shuttle, caliptra_aes)
+@@ -219,10 +219,10 @@ lazy val sodor = (project in file("generators/riscv-sodor"))
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
-
+ 
 -lazy val sha3 = (project in file("generators/sha3"))
 -  .dependsOn(rocketchip, midasTargetUtils)
 -  .settings(libraryDependencies ++= rocketLibDeps.value)
@@ -23,6 +23,6 @@ index 302d99e6..0aa0fcb4 100644
 +//   .dependsOn(rocketchip, midasTargetUtils)
 +//   .settings(libraryDependencies ++= rocketLibDeps.value)
 +//   .settings(commonSettings)
-
+ 
 lazy val gemmini = (project in file("generators/gemmini"))
   .dependsOn(rocketchip)
--- a/scripts/uniquify-module-names.py
+++ b/scripts/uniquify-module-names.py
@@ -109,7 +109,7 @@ def generate_copy(c, sfx):
  new_file = os.path.join(args.gcpath, new_file)

  shutil.copy(cur_file, new_file)
-  bash(f"sed -i s/\"module {cur_name}\"/\"module {new_name}\"/ {new_file}")
+  bash(f"sed -i 's/module\( \+\){cur_name}/module\\1{new_name}/' {new_file}")
  return new_file

 def bfs_uniquify_modules(tree, common_fnames, verilog_module_filename):
@@ -136,7 +136,7 @@ def bfs_uniquify_modules(tree, common_fnames, verilog_module_filename):
        new_file = generate_copy(cur_file, MODEL_SFX)
        if parent is not None and ((parent, mod) not in updated_submodule):
          parent_file = os.path.join(args.gcpath, verilog_module_filename[parent])
-          bash(f"sed -i s/\"{mod} \"/\"{mod}_{MODEL_SFX} \"/ {parent_file}")
+          bash(f"sed -i 's/\( \*\){mod}\( \+\)/\\1{mod}_{MODEL_SFX}\\2/' {parent_file}")
          updated_submodule.add((parent, mod))

        # add the uniquified module to the verilog_modul_filename dict
--- a/scripts/utils.sh
+++ b/scripts/utils.sh
@@ -53,3 +53,27 @@ function restore_bash_options
 {
    set +vx; eval "$OLDSTATE"
 }
+
+#######################################
+# Wrapper around replace-content.py.
+# For a file ($1), write out text ($3) into it
+# replacing any area designated by $2.
+#######################################
+function replace_content
+{
+    # On macOS, use GNU readlink from 'coreutils' package in Homebrew/MacPorts
+    if [ "$(uname -s)" = "Darwin" ] ; then
+        READLINK=greadlink
+    else
+        READLINK=readlink
+    fi
+
+    # If BASH_SOURCE is undefined, we may be running under zsh, in that case
+    # provide a zsh-compatible alternative
+    DIR="$(dirname "$($READLINK -f "${BASH_SOURCE[0]:-${(%):-%x}}")")"
+    file="$1"
+    shift
+    key="$1"
+    shift
+    $DIR/replace-content.py "$file" "$key" "$@"
+}
--- a/tests/Makefile
+++ b/tests/Makefile
@@ -2,14 +2,14 @@
 # RISCV Toolchain
 #################################

-PREFIX = riscv64-unknown-elf-
+TARGET = riscv64-unknown-elf

-GCC = $(PREFIX)gcc
-CXX = $(PREFIX)g++
-CP = $(PREFIX)objcopy
-OBJDUMP = $(PREFIX)objdump
-DG = $(PREFIX)gdb
-SIZE = $(PREFIX)size
+GCC = $(TARGET)-gcc
+CXX = $(TARGET)-g++
+CP = $(TARGET)-objcopy
+OBJDUMP = $(TARGET)-objdump
+DG = $(TARGET)-gdb
+SIZE = $(TARGET)-size


 #################################
--- a/tests/blkdev.c
+++ b/tests/blkdev.c
@@ -59,8 +59,8 @@ void blkdev_write(unsigned long offset, void *addr, size_t nsectors)
 #define TEST_NSECTORS 4
 #define TEST_SIZE (TEST_NSECTORS * BLKDEV_SECTOR_SIZE / sizeof(int))

-unsigned int test_data[TEST_SIZE];
-unsigned int res_data[TEST_SIZE];
+unsigned int test_data[TEST_SIZE] __attribute__ ((aligned (64)));
+unsigned int res_data[TEST_SIZE]  __attribute__ ((aligned (64)));

 int main(void)
 {
--- a/tests/gcd.c
+++ b/tests/gcd.c
@@ -1,9 +1,9 @@
 #include "mmio.h"

-#define GCD_STATUS 0x1000
-#define GCD_X 0x1004
-#define GCD_Y 0x1008
-#define GCD_GCD 0x100C
+#define GCD_STATUS 0x4000
+#define GCD_X 0x4004
+#define GCD_Y 0x4008
+#define GCD_GCD 0x400C

 unsigned int gcd_ref(unsigned int x, unsigned int y) {
  while (y != 0) {
--- a/tests/libgloss.mk
+++ b/tests/libgloss.mk
@@ -5,6 +5,10 @@ ifndef GCC
 $(error GCC is not defined)
 endif

+ifndef TARGET
+$(error TARGET is not defined)
+endif
+
 libgloss_specs := htif_nano.specs

 # Test whether libgloss-htif is globally installed and usable
--- a/tools/barstools
+++ b/tools/barstools
--- a/tools/install-circt
+++ b/tools/install-circt
--- a/variables.mk
+++ b/variables.mk
@@ -293,11 +293,12 @@ endif
 # build output directory for compilation
 #########################################################################################
 # output for all project builds
-gen_dir=$(sim_dir)/generated-src
+generated_src_name ?=generated-src
+gen_dir             =$(sim_dir)/$(generated_src_name)
 # per-project output directory
-build_dir=$(gen_dir)/$(long_name)
+build_dir           =$(gen_dir)/$(long_name)
 # final generated collateral per-project
-GEN_COLLATERAL_DIR ?= $(build_dir)/gen-collateral
+GEN_COLLATERAL_DIR ?=$(build_dir)/gen-collateral

 #########################################################################################
 # assembly/benchmark variables
--- a/vlsi/Makefile
+++ b/vlsi/Makefile
@@ -42,7 +42,7 @@ HAMMER_EXEC        ?= $(if $(filter $(tech_name),sky130),\
                        ./example-vlsi-sky130,\
                        ./example-vlsi)
 VLSI_TOP           ?= $(TOP)
-VLSI_MODEL_DUT_NAME ?= chiptop
+VLSI_MODEL_DUT_NAME ?= chiptop0
 # If overriding, this should be relative to $(vlsi_dir)
 VLSI_OBJ_DIR       ?= build
 ifneq ($(CUSTOM_VLOG),)
--- a/vlsi/sim.mk
+++ b/vlsi/sim.mk
@@ -51,7 +51,11 @@ $(SIM_DEBUG_CONF): $(sim_common_files) check-binary
 	mkdir -p $(dir $@)
 	mkdir -p $(output_dir)
 	echo "sim.inputs:" > $@
-	echo "  defines: ['DEBUG']" >> $@
+	echo "  defines:" >> $@
+	echo "    - 'DEBUG'" >> $@;
+ifndef USE_VPD
+	echo "    - 'FSDB=1'" >> $@;
+endif
 	echo "  defines_meta: 'append'" >> $@
 	echo "  execution_flags:" >> $@
 	for x in $(VERBOSE_FLAGS) $(call get_waveform_flag,$(call get_sim_out_name,$(BINARY))); do \
--- a/vlsi/tutorial.mk
+++ b/vlsi/tutorial.mk
@@ -12,6 +12,7 @@ ifeq ($(tutorial),asap7)
    TECH_CONF         ?= example-asap7.yml
    DESIGN_CONFS      ?=
    VLSI_OBJ_DIR      ?= build-asap7-commercial
+    INPUT_CONFS       ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONFS) $(EXTRA_CONFS)
 endif

 ifeq ($(tutorial),sky130-commercial)
@@ -23,6 +24,7 @@ ifeq ($(tutorial),sky130-commercial)
                        $(if $(filter $(VLSI_TOP),Rocket), \
                            example-designs/sky130-rocket.yml, )
    VLSI_OBJ_DIR      ?= build-sky130-commercial
+    INPUT_CONFS       ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONFS) $(EXTRA_CONFS)
 endif

 ifeq ($(tutorial),sky130-openroad)
@@ -36,8 +38,8 @@ ifeq ($(tutorial),sky130-openroad)
                        $(if $(filter $(VLSI_TOP),RocketTile), \
                            example-designs/sky130-openroad-rockettile.yml, )
    VLSI_OBJ_DIR      ?= build-sky130-openroad
+    INPUT_CONFS       ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONFS) $(EXTRA_CONFS)
    # Yosys compatibility for CIRCT-generated Verilog, at the expense of elaboration time.
    ENABLE_YOSYS_FLOW  = 1
 endif

-INPUT_CONFS       ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONFS) $(EXTRA_CONFS)