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Author SHA1 Message Date
Paul RiggeandJohn Wright 22e6d9c5d4 Fix repl-seq-mem 2019-02-13 10:15:51 -08:00
Paul RiggeandJohn Wright 7bbf7f00f6 Run transforms in slightly different order 
Also, don't rename TestHarness.
 2019-02-13 10:15:51 -08:00
Paul RiggeandJohn Wright 801abd98bb Fix null pointer exception in options parser 2019-02-13 10:15:51 -08:00
Paul RiggeandJohn Wright f310d45381 Refactor barstools for new versions of things. 
- No handlebars (not being published for Scala 2.12)
- Update for new annotations APIs

Bump sbt-dependency-graph to 0.9.2 for this scala version
 2019-02-13 10:15:51 -08:00
Edward Wangandedwardcwang 4727d475c7 Add options to force certain memories to lib or synflops 2019-02-06 12:40:53 -08:00
Edward Wangandedwardcwang d1c1b3fba6 Overhaul CompilerMode parsing 2019-02-06 12:40:53 -08:00
edwardcwangandGitHub 74ca2bc491 Remove deprecated run-main 2018-10-31 13:47:28 -07:00
edwardcwangandGitHub 93bf7895be Fix corner case in compiling a small mem using a large lib (#32) 
* Refactor bit pairs calculation into a separate function

* Minor clarifications

* Clarify MacroCompilerSpec helpers

* Add SmallTagArrayTest test

* Fix corner case in compiling a small mem using a large lib
 2018-04-26 10:33:55 -07:00
edwardcwangandGitHub f7634b82cd Include macro compiler JAR compilation instructions 2018-03-21 14:50:18 -07:00
Edward Wang 1ccd8f6dbc Bump mdf to match master 2018-02-16 16:03:08 -08:00
Adam IzraelevitzandGitHub 79c8c283cc Add memory compiler to macros (#29) 
* Add memory compiler to macros

* Removed weird spacing

* Make sramcompiler width/depth range inclusive

* Added sramcompiler test
 2018-02-16 16:01:10 -08:00
edwardcwangandGitHub 8a30579a3e Support firrtl output in command line for MacroCompiler (#28) 
* Use the given port prefix (fix a bug preventing two unit tests from passing)
* Support firrtl output in addition to Verilog
 2017-12-04 15:12:42 -08:00
edwardcwangandGitHub c884a2fb15 Correct multi-ported memory compilation (#27) 
* Correct multi-ported memory compilation

It was incorrectly splitting multiple times before. Fixed the issue and
added regression tests for this issue.

* Add 1 read 1 write test
 2017-10-06 18:04:49 -07:00
Edward Wangandedwardcwang e1499fcdc0 Update command line help 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang c91d98d5b3 Bump mdf for the last time, for now 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang e09f8b1b0d Fix grammar 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang bc26f5eb1a Address review comments 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang d2b105079d Not a scaladoc 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang 4eca53ba55 Bump mdf again 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang 13d8a0f8f5 Add strict mode 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang 11bd81165b Bump mdf 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang 43d242707b Enable some more tests 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang af67540a81 Add test from Donggyu 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang 5d3bebd2b9 Re-implement parallel mapping 
- Support byte-masked SRAM, yay
- Also nuke a bunch of bugs
 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang 676b8e72ba Add rocket-chip inspired tests 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang e726daec41 Bump mdf 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang e89079f2d7 Test for non-empty Verilog 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang f9edbfea27 Move cost metric to its own file 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang df8b5815c6 Trim redundant MDF field 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang 4013b1924f Implement command line cost metric selection 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang 0f4683700f Add cost function selection test 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang 0203aa9e7c Move notes to main file since they apply there as well 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang a25c84f72c Specify cost function from command line 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang 923a08dfa1 Fix typo 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang 00c99f56b1 Add sbt-assembly for making jar 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang ffd7893d63 Implement cost selection from command line 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang 0e474dac5e Add external metric 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang 122e433e94 Bump mdf again 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang 5d14f1995a Start cost function refactor 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang 0f2d00e008 Add some documentation 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang f854c6c9f0 Nuke hardcoded JSON tests from orbit 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang a177c895e8 Finish rewriting in new format 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang 513da4eb37 Support non-prefixed ports 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang a0e817b6fb Bump mdf 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang 85d18b736e Document 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang 519ffef50a Tests aren't that brittle since firrtl reparses the output 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang e47cf92139 Move HasNoLibTestGenerator out of SynFlops 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang 94b13e96fb Add functional tests 
To be enabled when a new firrtl-interpreter is published
 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang de66405fe8 Write flop tests using generator 2017-10-03 11:56:30 -07:00
Edward Wangandedwardcwang 93331cd26d More refactor 2017-10-03 11:56:30 -07:00