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Author SHA1 Message Date
Colin Schmidt
5bfc289677 Bump fesvr for better loadmem impl. Fix verilator loadmem support 2020-08-05 10:05:02 -07:00
Colin Schmidt
93c7fef942 We need to uppercase hex chars for bc 2020-08-05 10:03:21 -07:00
Howard Mao
09cc1bb985 Merge pull request #635 from ucb-bar/loadmem 
Implement fast loadmem feature
 2020-08-04 15:39:45 -07:00
Howard Mao
813d1fdb9e bump firesim 2020-08-03 16:09:16 -07:00
Jerry Zhao
3c4c4a1ad3 Merge pull request #630 from banahogg/patch-1 
Update BOOM URL in README.md
 2020-08-03 14:47:02 -07:00
Jerry Zhao
c7586be0c5 Merge pull request #629 from ucb-bar/random-seed 
Add RANDOM_SEED variable to set random init for VCS and Verilator simulations
 2020-08-03 14:46:16 -07:00
Howard Mao
d7f3f91f18 implement fast loadmem feature 2020-08-01 15:04:18 -07:00
ssteffl
2e3b871beb Merge pull request #636 from ucb-bar/openroad 
updated openroad hash
 2020-07-31 11:57:56 -07:00
Sam Steffl
16d4186ea4 updated openroad hash 2020-07-31 10:29:53 -07:00
ssteffl
88fceafb68 Merge pull request #608 from ucb-bar/openroad 
OpenROAD complete backend with nangate45
 2020-07-30 16:27:10 -07:00
Nathan Pemberton
29c924d45a Merge pull request #633 from ucb-bar/opensbi 
Opensbi
 2020-07-22 10:00:47 -07:00
Nathan Pemberton
df07790a5a Bump FireMarshal/QEMU/riscv-isa-sim for OpenSBI 2020-07-21 18:43:14 -07:00
Jerry Zhao
b719919934 Add RANDOM_SEED variable to set random init for VCS and Verilator simulations 2020-07-20 18:25:18 -07:00
Fang, Zitao
11c1e87638 Merge pull request #615 from ucb-bar/custom-core-doc 
Documentation for Third-Party Core Integration
 2020-07-20 11:56:56 -07:00
Zitao Fang
692b120b65 Fixed typo 2020-07-19 21:48:07 -07:00
Zitao Fang
0a39819f44 Add source file note 2020-07-19 21:46:32 -07:00
Zitao Fang
2c7e7f3199 Fixed file links 2020-07-19 21:36:50 -07:00
banahogg
ae1e44a9e3 Update BOOM URL in README.md 2020-07-18 17:44:52 -07:00
Zitao Fang
fddf218147 5th revision 2020-07-16 15:39:07 -07:00
Jerry Zhao
862d1fb774 Merge pull request #627 from ucb-bar/firrtl-logging 
Add variable to control FIRRTL logging verbosity
 2020-07-16 13:45:57 -07:00
Zitao Fang
97b8c3035c Merge branch 'dev' of github.com:ucb-bar/chipyard into custom-core-doc 2020-07-15 11:15:46 -07:00
Zitao Fang
9fbc0a5bea Add links 2020-07-15 11:08:36 -07:00
Zitao Fang
7ea464dc90 4th revision 2020-07-14 12:49:36 -07:00
Zitao Fang
14399e88b3 Minor change 2020-07-12 01:23:34 -07:00
Zitao Fang
ced7ea634c 3rd Revision 2020-07-12 01:08:13 -07:00
David Biancolin
d5a2d43f85 Merge pull request #612 from ucb-bar/zynq-target 
[firechip] Add a small target that should fit on all hosts
 2020-07-10 18:12:34 -07:00
Albert Ou
fbc71d4215 Merge pull request #625 from ucb-bar/uart 
Override default baud rate for FireChip
 2020-07-10 10:55:50 -07:00
Jerry Zhao
f8c9b316e2 Merge pull request #620 from ucb-bar/simple_configs 
Deduplicate across Chipyard configs into a ChipyardBaseConfig
 2020-07-09 17:12:19 -07:00
Jerry Zhao
2196a621c6 Pass FIRRTL_LOGLEVEL to GenerateTopAndHarness 2020-07-09 12:39:17 -07:00
Jerry Zhao
8124ce3df1 Add FIRRTL_LOGLEVEL variable 2020-07-09 12:38:21 -07:00
Jerry Zhao
7239e23185 Merge branch 'dev' into simple_configs 2020-07-09 11:31:33 -07:00
Jerry Zhao
11c87777fe Remove BOOM debug print 2020-07-09 11:29:58 -07:00
Albert Ou
84620e027b Merge pull request #626 from ucb-bar/testchipip 
Bump testchipip for bug fixes
 2020-07-08 23:01:35 -07:00
Zitao Fang
9ad9d00a23 Second revision 2020-07-08 16:02:31 -07:00
Albert Ou
763ba42b4c Bump testchipip for FDT alignment and minLatency fixes 2020-07-08 12:36:09 -07:00
Albert Ou
b55e579c91 Override default baud rate for FireChip 
This avoids target software needing to explicitly set the divisor to
match the UART bridge.
 2020-07-07 23:00:14 -07:00
Fang, Zitao
60f7ec60bd Merge pull request #588 from ucb-bar/ariane-decouple 
Test Suite Simplification
 2020-07-07 12:55:52 -07:00
alonamid
19152d3b73 Update README.md (#619) 2020-07-06 20:29:34 -07:00
Jerry Zhao
661038f992 Deduplicate across Chiypard configs into a ChipyardBaseConfig 2020-07-06 17:54:24 -07:00
Zitao Fang
6cb8a60a80 Remove Key List 2020-07-05 21:18:31 -07:00
Zitao Fang
744e73fa92 Editing Docs 2020-07-05 21:05:21 -07:00
Jerry Zhao
d3721bbd99 Merge pull request #618 from ucb-bar/mmio_fix 
Fixes for AXI4 MMIO and FBus ports
 2020-07-03 12:15:50 -07:00
Jerry Zhao
a7047c4ba2 Fix FireChip BridgeBinders 2020-07-03 08:33:10 -07:00
Zitao Fang
104c350a59 Custom Core Integration Doc, 1st Revision 2020-07-02 15:56:15 -07:00
Jerry Zhao
863f723708 Pipe through AXI4 MMIO and Slave ports to ChipTop | IOBinders fix 
* Fixes bug with AXI4 MMIO ports not being generated properly due to
   IOBinders issue. Additionally adds IOCells to AXI4 ports so that they
   appear in ChipTop
 * Change IOBinders to also require passing p: Parameters
   to child functions. Serialization of type targets via ClassTags fails
   for compound types, so we cannot use `BaseSubsystem with HasSomeTrait`
   as the type target in OverrideIOBinders.
 2020-06-30 13:42:06 -07:00
Zitao Fang
d77c4afb36 Rollback .gitignore 2020-06-29 12:05:24 -07:00
Zitao Fang
c85d8c4211 Remove generic parameter from this PR 2020-06-29 11:42:34 -07:00
Zitao Fang
d9556e14f5 Merge branch 'dev' of github.com:ucb-bar/chipyard into ariane-decouple 2020-06-28 21:39:32 -07:00
Zitao Fang
7b5f474b04 Finished Custom Core Docs 2020-06-28 21:26:50 -07:00
Zitao Fang
42f93ff32d Merge branch 'dev' of github.com:ucb-bar/chipyard into custom-core-doc 2020-06-28 21:26:09 -07:00