 Jerry Zhao
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93e57ef230
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Make the ChipTop reset pin async always
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2020-10-26 15:18:34 -07:00 |
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Jerry ZhaoandGitHub
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d61b31a6fe
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Merge pull request #702 from ucb-bar/multirocc-gemmini
Add MultiRoCCGemmini config fragment
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2020-10-26 10:03:26 -07:00 |
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Fang, ZitaoandGitHub
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4fdb9eb6b0
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Merge pull request #647 from ucb-bar/verilator-makefile-fix
Fix Verilator Simulation run-binary-debug Error
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2020-10-23 21:54:58 -07:00 |
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Zitao Fang
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abbeb2af9e
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Fixed comments
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2020-10-23 17:00:56 -07:00 |
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Zitao Fang
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0c4dcffb0d
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Fixed lowercase p bug
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2020-10-23 16:39:56 -07:00 |
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Jerry ZhaoandGitHub
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ac19117ec5
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Add MultiRoCCGemmini config fragment
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2020-10-23 15:41:49 -07:00 |
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Abraham Gonzalez
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a07369acaf
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Merge remote-tracking branch 'ch/lazy-iobinders' into local-fpga-temp
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2020-10-20 21:23:11 -07:00 |
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Jerry Zhao
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7a55c55aa3
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Fix no-MBUS configs
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2020-10-20 01:12:28 -07:00 |
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Jerry Zhao
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e0bf907a06
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Merge remote-tracking branch 'origin/dev' into lazy-iobinders
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2020-10-19 13:22:01 -07:00 |
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Abraham Gonzalez
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dd358f45ab
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UART Working... Bumped to newer fpga-shells
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2020-10-19 11:29:25 -07:00 |
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Jerry Zhao
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f3d666d2b7
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Clarify HarnessBinders ClassTag naming
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2020-10-19 10:16:44 -07:00 |
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Jerry Zhao
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9927231bc4
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Support lazy-iobinders
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2020-10-17 22:47:50 -07:00 |
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David Biancolin
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1b94e7f10c
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Merge remote-tracking branch 'origin/dev' into diplomatic-clocks-mbus-crossing
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2020-10-16 23:21:20 +00:00 |
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Alon Amid
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6eaac63e1b
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address PR comments
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2020-10-16 06:34:26 +00:00 |
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Albert Magyar
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84e0bf7338
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Don't annotate cores with FAMEModelAnnotations
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2020-10-15 12:25:39 -07:00 |
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abejgonzalez
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9ba4918cb8
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Inject MMCDevice into TLSPI Node
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2020-10-15 11:46:42 -07:00 |
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David Biancolin
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74c1c9d7ab
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Punch out reset in AXI4MMIO IOBinder
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2020-10-15 11:28:36 -07:00 |
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Alon Amid
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2c935b4ad7
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pull firesim mem model config into firesim tweaks
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2020-10-15 17:07:51 +00:00 |
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Alon Amid
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4a317b0cab
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differentiate default config package delimiter
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2020-10-15 17:07:20 +00:00 |
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David Biancolin
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9c8d2948af
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[firechip] Fix a broken config
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2020-10-14 15:33:32 -07:00 |
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David Biancolin
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6aefb73ab5
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Merge remote-tracking branch 'origin/dev' into diplomatic-clocks-mbus-crossing
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2020-10-14 15:29:00 -07:00 |
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abejgonzalez
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949d60597f
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Revert "Support evaluation of HarnessBinders in LazyModule context"
This reverts commit 9c298eedfe.
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2020-10-14 14:50:38 -07:00 |
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abejgonzalez
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dda7622c29
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temp commit
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2020-10-14 14:49:22 -07:00 |
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David Biancolin
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211c33f996
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Address comments in #690
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2020-10-14 14:42:45 -07:00 |
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abejgonzalez
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341a6cc48d
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Merge remote-tracking branch 'origin/lazy-harnessbinders' into local-fpga-temp
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2020-10-13 16:23:41 -07:00 |
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abejgonzalez
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5bbd865447
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Add MMC Device section to the DTS
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2020-10-13 16:18:00 -07:00 |
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Jerry Zhao
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9c298eedfe
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Support evaluation of HarnessBinders in LazyModule context
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2020-10-13 15:10:41 -07:00 |
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Jerry Zhao
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0c46ed1676
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Rename testchip_fesvr to testchip_tsi
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2020-10-09 09:34:20 -07:00 |
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Jerry Zhao
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25129c27ca
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Add testchip_fesvr to uncondtionally used resources
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2020-10-09 09:27:58 -07:00 |
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Jerry Zhao
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d71c3b6357
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Unify htif implementation with firesim
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2020-10-09 09:27:58 -07:00 |
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David Biancolin
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986b5831c8
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[clocking] Sketch out a topology that puts the MBUS is a separate domain
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2020-10-09 07:23:17 -07:00 |
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David Biancolin
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30b278687b
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[clocking] Also aggregate clocks in AsyncClockGroup
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2020-10-09 07:13:55 -07:00 |
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dunn
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252f9c6a12
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Beginning to modify Arty TestHarness to conform with HarnessBinders. Currently does not compile; debugging.
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2020-10-07 11:55:16 -07:00 |
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David Biancolin
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392d5b0801
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[clocking] Synchronize all output clocks from DividerOnly generator
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2020-10-07 09:32:48 -07:00 |
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dunn
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a67318928a
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Bumping submodules to upstream dev's commits.
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2020-10-07 09:02:30 -07:00 |
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Zitao Fang
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5282965b5b
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Filter specified HTIF arguments and plusargs only
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2020-10-06 15:50:11 -07:00 |
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dunn
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309b9ee7ae
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Merge remote-tracking branch 'upstream/dev' into local-fpga-arty-abe
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2020-10-06 12:23:18 -07:00 |
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Zitao Fang
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355e4ba606
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Change to filter all arguments that begin with a '-'
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2020-10-05 10:49:04 -07:00 |
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Jerry Zhao
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3d0022667a
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Bump testchipip
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2020-10-01 22:43:43 -07:00 |
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Jerry Zhao
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b057cfbd8c
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Merge remote-tracking branch 'origin/dev' into clocking-features
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2020-10-01 20:12:20 -07:00 |
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Jerry ZhaoandGitHub
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2db3c90f83
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Merge pull request #648 from ucb-bar/sodor-integrate
Sodor Integration
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2020-10-01 17:31:45 -07:00 |
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Jerry Zhao
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79042e4ce8
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Bump to support firesim simulation of no-AXI4DRAM designs
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2020-10-01 10:21:43 -07:00 |
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Jerry Zhao
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164617e2d6
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Fix no-mbus example design
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2020-10-01 10:20:10 -07:00 |
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Jerry Zhao
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489ae695fc
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Add tile-resetter to all designs
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2020-10-01 10:19:43 -07:00 |
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Zitao Fang
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6c33672c66
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Bump Sodor submodule after merge
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2020-10-01 10:08:39 -07:00 |
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Albert Magyar
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2f5790d611
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Add model multi-threading annotations (ignored by default) to FireChip
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2020-09-30 23:32:49 -07:00 |
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Zitao Fang
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ef03a5efe0
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Bump testchipip
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2020-09-30 14:36:45 -07:00 |
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David Biancolin
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ebfe3103a4
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[clocks] IdealizedPll -> DividerOnlyClockGenerator
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2020-09-29 17:33:49 -07:00 |
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David Biancolin
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5b414f5829
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[clocks] Emit frequency summary for divider-only PLL model
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2020-09-29 16:59:37 -07:00 |
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David Biancolin
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a6ce850391
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[clocks] ClockDividerN: make first output edge occur on first input edge
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2020-09-29 16:19:05 -07:00 |
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