* [uart] add uart adapter | add uart + adapter to all configs
* [uart] change pty define name | add uart to all configs that need it
* [uart] default to 115200 baudrate
* [dromajo] first working commit
* [dromajo] bump boom for commit-width > 1 fix
* [dromajo] adjust dromajo commits
* [dromajo] bump boom
* commit dromajo changes
* extra
* [dromajo] add block device to configs
* rebump older modules
* bump firesim
* [chipyard] enable dromajo in midas level simulation
* [testchipip] forgot to bump
* get rid of breaking things
* bump firesim
* bump boom
* Bump BOOM to ifu3 WIP
* bump firesim
* fix how memory is passed to dromajo
* bump boom and firesim
* fix merge issues
* add dromajo cosim bridge in chipyard
* move traceio back into testchipip (#488)
* refer to testchipip traceio in firechip (#490)
* Move TraceIO fragment to chipyard (#492)
* fix chipyard dromajo bridge (#493)
* Sboom dromajo bump (#501)
* [FireChip] Use clock in BridgeBinders
* [firesim] Update TraceGen BridgeBinder
* [Firechip] Add support for Tile <-> Uncore rational division
* [firesim] Update the multiclock test
* [firechip] Commit some Eagle X-related mock configs
* [firechip] Instantiate multiple TracerV bridges
* [Firechip] Include reset in tracerv tokens
* [TracerV] Drop the first token in comparison tests
* [Firechip] Make reverse instruction order in trace printf
* WARNING: Point at a fork of boom @ davidbiancolin
* [firesim] Update ClockBridge API
* Add Gemmini to README [ci skip] (#487)
* [firechip] Isolate all firesim-multiclock stuff in a single file
* add documentation on ring network and system bus
* Bump firesim for CI
* Bump FireSim
* Bump testchipip to dev
[ci skip]
* Bump FireSim
* [make] split up specific make vars/targets into frags (#499)
* [make] split up specific make vars/targets into frags
* [make] move dramsim and max-cycles into SIM_FLAGS
* [misc] move ariane configs to configs/ folder
* [dromajo] add dromajo
* [dromajo] bump for new traceio changes
* bump firesim
* bump firesim
* point to chipyard traceio
* bump boom
Co-authored-by: David Biancolin <david.biancolin@gmail.com>
Co-authored-by: Howard Mao <zhehao.mao@gmail.com>
* Support Dromajo + TracerV configurations
* [docs] add documentation for Dromajo in FireSim + Chipyard
* add a bit more docs
* [docs] bump docs
* [firesim] dump artefacts in firesim
* [firesim] update firesim
* [testchipip] remove extraneous items in testchipip
* [dromajo] prevent dromajo from breaking when params unset
* update firesim, dromajo, and testchipip
* [firesim] bump firesim
* [firesim] bump firesim
* [misc] bump firesim and testchipip for reviewer comments
* remove WithNoGPIO fragment
* bump firesim
* bump dromajo boom config
* bump firesim
* generate artefacts in firesim testsuite
Co-authored-by: abejgonzalez <abe.j.gonza@gmail.com>
Co-authored-by: Abraham Gonzalez <abe.gonzalez@berkeley.edu>
Co-authored-by: David Biancolin <david.biancolin@gmail.com>
Co-authored-by: Howard Mao <zhehao.mao@gmail.com>
[WIP] Minimally elaborating design
Bring up a feature-complete Chipyard stage
Pull in Makefrag generation; Bump submodules
Update config generation, and global reset scheme
Bump submodules; clean up
Bump FireSim
Remove some unhygenic comments / WS
Remove the rocketchip subproject
[CI] Lengthen ariane tests timeout
Address some remaining reviewer comments
[firechip] Refresh a Field that cannot be used across repeated instantiations
Bump all submodules
This adds an additional layer (ChipTop) between the System module and the TestHarness. The IOBinder API is now changed to take only a single parameter (an Any) and return a 3 things: The IO port(s), the IO cell(s), and a function to call inside the test harness, which is analogous to the old IOBinder function, except that it takes a TestHarness object as an argument instead of (clock, reset, success).
* A new Top-level module, ChipTop, has been created. ChipTop instantiates a "system" module specified by BuildSystem.
* BuildTop now builds a ChipTop dut module in the TestHarness by default
* A new BuildSystem key has been added, which by default builds DigitalTop (previously just called Top)
* The IOBinders API has changed. IOBinders are now called inside of ChipTop and return a tuple3 of (IO ports, IO cells, harness functions). The harness functions are now called inside the TestHarness (this is analogous to the previous IOBinder functions).
* IO cell models have been included in ChipTop. These can be replaced with real IO cells for tapeout, or used as-is for simulation.
* The default for the TOP make variable is now ChipTop (was Top)
* [ariane/make] integrate ariane | have verilator be installed on path not in makefile
* [misc] warn on verilator not found | search for v files | cleanup build.sbt + .gitignore
* [firesim] bump
* [ci] add midas ariane tests
* [docker/ci] use new docker-image with verilator | re-elab on v changes for ariane | address comments
* [ci] remove references to local verilator install
* [verilator] update flags
* [verilator] minimal set of flags for ariane
* [ariane] bump ariane to master
* [ci] revert to 4.016 verilator
* [ci] install verilator to ci server | misc compile fixes
* [ci/make] add longer ci timeout | update when assert is added in verilator sim
* [firesim] bump for misc. updates
* [make/ci] cleanup makefile and remove firesim tests of it
* [docs/firesim] bump and clean docs
* [firesim] bump
* [ci] use remote verilator for midas tests
* [misc] cleanup built.sbt more
* [firesim] bump
* [misc] bump build.sbt patch for tutorials
* [firesim/ci] cleanup and bump firesim
* Bump all submodules for chisel 3.2.0 and rocket-chip august-2019
* Fix subprojects that aren't tested from normal sims
* Fix firechip for chisel 3.2.0 and rc bump
* Bump boom for bug fix rebase
* [sbt] Don't rely on target-rtl symlink when FireSim is top [no ci]
* Bump boom for rc bump fix to bug fix
* Bump FireSim for CI check
* Bump FireSim
* Bump submodules after merge
