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134 Commits

Author SHA1 Message Date
Albert Magyar
f7a98f23bc Merge pull request #756 from ucb-bar/16-largeboom 
Add 16-core LargeBOOM config to firechip
 2021-01-13 15:36:51 -08:00
Albert Magyar
c481dc2ee8 Add 16-core LargeBOOM config to firechip 
* Fix Jerry's comment on accidentally mixing multiple BOOM configs
 2021-01-12 23:12:10 -08:00
David Biancolin
1bd51447fe [ci skip] Fix Typo in firechip/src/test/scala/ScalaTestSuite.scala 
Co-authored-by: Abraham Gonzalez <abe.j.gonza@gmail.com>
 2020-12-13 10:45:51 -05:00
David Biancolin
8f1e20936f Update FireSim CI. Push threading into test context 2020-12-12 13:41:32 -08:00
David Biancolin
ee436c9b3f [firechip] Fix a uart multiclock bug 2020-12-10 07:18:12 +00:00
David Biancolin
230bd81e0e [firechip] Update legacy firechip config 2020-11-09 09:26:30 -08:00
Abraham Gonzalez
5c5a4b51e3 Merge pull request #710 from ucb-bar/rename-ariane 
Rename Ariane to CVA6
 2020-11-06 14:53:54 -08:00
abejgonzalez
a2ebbee2ac Rename Ariane to CVA6 2020-11-04 15:42:30 -08:00
David Biancolin
f504b7a0f5 [clocking] Improve reference clock selection using a multiple-of-fastest strategy 2020-11-03 09:14:55 -08:00
Jerry Zhao
e0bf907a06 Merge remote-tracking branch 'origin/dev' into lazy-iobinders 2020-10-19 13:22:01 -07:00
Jerry Zhao
9927231bc4 Support lazy-iobinders 2020-10-17 22:47:50 -07:00
David Biancolin
1b94e7f10c Merge remote-tracking branch 'origin/dev' into diplomatic-clocks-mbus-crossing 2020-10-16 23:21:20 +00:00
Albert Magyar
84e0bf7338 Don't annotate cores with FAMEModelAnnotations 2020-10-15 12:25:39 -07:00
Alon Amid
2c935b4ad7 pull firesim mem model config into firesim tweaks 2020-10-15 17:07:51 +00:00
David Biancolin
9c8d2948af [firechip] Fix a broken config 2020-10-14 15:33:32 -07:00
David Biancolin
6aefb73ab5 Merge remote-tracking branch 'origin/dev' into diplomatic-clocks-mbus-crossing 2020-10-14 15:29:00 -07:00
David Biancolin
211c33f996 Address comments in #690 2020-10-14 14:42:45 -07:00
David Biancolin
986b5831c8 [clocking] Sketch out a topology that puts the MBUS is a separate domain 2020-10-09 07:23:17 -07:00
David Biancolin
392d5b0801 [clocking] Synchronize all output clocks from DividerOnly generator 2020-10-07 09:32:48 -07:00
Jerry Zhao
b057cfbd8c Merge remote-tracking branch 'origin/dev' into clocking-features 2020-10-01 20:12:20 -07:00
Jerry Zhao
79042e4ce8 Bump to support firesim simulation of no-AXI4DRAM designs 2020-10-01 10:21:43 -07:00
Albert Magyar
2f5790d611 Add model multi-threading annotations (ignored by default) to FireChip 2020-09-30 23:32:49 -07:00
David Biancolin
5b414f5829 [clocks] Emit frequency summary for divider-only PLL model 2020-09-29 16:59:37 -07:00
David Biancolin
b76972d34b Merge remote-tracking branch 'origin/dev' into diplomatic-clocks-pll-redux 2020-09-25 11:02:51 -07:00
David Biancolin
67145c6ccd [clocking] Fix FireSim clock look up 2020-09-25 10:05:28 -07:00
David Biancolin
7b8a954d04 [firechip] Rework FireSim clocking to be more similar to default CY targets 2020-09-24 23:32:07 -07:00
Jerry Zhao
0d8e87126c Deprecate support for on-chip SerialAdapter 2020-09-14 19:43:32 -07:00
Jerry Zhao
f9cc1dc2c2 Merge remote-tracking branch 'origin/dev' into serial-tl 2020-09-14 19:35:43 -07:00
Jerry Zhao
10625a3a6c Undo regression in iocells flexibility 2020-09-14 13:27:31 -07:00
Jerry Zhao
6c5bce5430 Support Tilelink over serial 2020-09-13 11:59:16 -07:00
Jerry Zhao
a5385c0a54 Update testchipip/icenet to use rocket-chip Located API 2020-09-11 00:02:07 -07:00
Jerry Zhao
facef464e6 Update BridgeBinders | fix runtime HarnessBinder port type checks 2020-09-09 00:15:02 -07:00
Jerry Zhao
0f50e4d118 Split IOBinders into IOBinders and Harness Binders | punch out clocks to harness for simwidgets and bridges 2020-09-04 15:20:13 -07:00
Jerry Zhao
3258fd8db8 Remove JTAG from firesim comfigs due to @(posedge ~clk) issue 2020-09-03 23:53:51 -07:00
Jerry Zhao
e275a45890 Address PR comments 2020-08-26 12:34:46 -07:00
Jerry Zhao
abc75e9b95 Fix Reset bug 2020-08-07 17:50:23 -07:00
Jerry Zhao
578ae6fca2 Bump to July 2020 rocketchip 2020-08-04 14:00:02 -07:00
Jerry Zhao
fdfef878af Merge branch 'dev' into diplomatic-clocks 2020-07-21 11:21:51 -07:00
David Biancolin
d5a2d43f85 Merge pull request #612 from ucb-bar/zynq-target 
[firechip] Add a small target that should fit on all hosts
 2020-07-10 18:12:34 -07:00
Albert Ou
b55e579c91 Override default baud rate for FireChip 
This avoids target software needing to explicitly set the divisor to
match the UART bridge.
 2020-07-07 23:00:14 -07:00
Jerry Zhao
56e1aeb400 Support FireSim diplomatic multiclock 2020-07-07 20:54:31 -07:00
Jerry Zhao
a7047c4ba2 Fix FireChip BridgeBinders 2020-07-03 08:33:10 -07:00
Jerry Zhao
863f723708 Pipe through AXI4 MMIO and Slave ports to ChipTop | IOBinders fix 
* Fixes bug with AXI4 MMIO ports not being generated properly due to
   IOBinders issue. Additionally adds IOCells to AXI4 ports so that they
   appear in ChipTop
 * Change IOBinders to also require passing p: Parameters
   to child functions. Serialization of type targets via ClassTags fails
   for compound types, so we cannot use `BaseSubsystem with HasSomeTrait`
   as the type target in OverrideIOBinders.
 2020-06-30 13:42:06 -07:00
David Biancolin
1dd3ea4aeb Update TargetConfigs.scala 2020-06-27 13:44:52 -07:00
David Biancolin
486cc5fce1 [firechip] Add a small target that should fit on all hosts 2020-06-20 13:57:11 -07:00
Jerry Zhao
d245df9133 Bump Rocketchip to June 2020 for Tile changes 2020-06-18 17:25:31 -07:00
David Biancolin
fa2d620fb2 Remove commented code in ScalaTests 2020-05-19 00:50:14 +00:00
David Biancolin
96e838c773 [firechip] Set the cover property library in FireSim Harnesses 2020-05-17 00:18:54 +00:00
David Biancolin
99846c1ccb [firechip] Use the standard Chipyard generator 2020-05-17 00:18:17 +00:00
Abraham Gonzalez
85b555dbce NVDLA Integration + Cleanup Ariane Preprocessing (#505) 
* [nvdla] initial nvdla integration

* [nvdla] add firesim configs

* [nvdla] re-add accidentally deleted line

* [nvdla] works on master with small

* [nvdla] use master branch of nvdla

* [nvdla] remove extra sources

* [nvdla] bump

* [nvdla + ariane] bump and use insert-includes for pre-processing

* [nvdla] add ci | remove target configs in FireChip | update naming

* [nvdla] bump nvdla | fix ci run-tests error

* [nvdla] re-enable PCWM-L error | fix/update makefile(s)

* [nvdla] bump nvdla fragments in FireChip

* [misc] bump tutorial patches

* [chipyard] remove extra import

* [nvdla] bump nvdla for pbus [ci skip]

* [nvdla] update firemarshal and add nvdla workload

* [nvdla] bump nvdla-workload

* [nvdla] bump hw

* [docs] add basic documentation

* [docs] adjustments to documentation

* [misc] update docs | bump firesim with recipe

* [misc] disable error on warnings in verilator | bump number width to match RC

* [docs] fix doc build error

* [verilator] move no fail on warning to be global

* [ci skip] [nvdla] bump submodule urls

* [misc] move firesim specific configs into nvdla dir [ci skip]

* [nvdla] fix run-tests in ci

* update RC configs | bump marshal | bump nvdla-workload

* [nvdla] bump nvdla-workload [ci skip]

* add topology mixin to nvdla configs

* update tutorial patches
 2020-05-16 12:22:30 -07:00