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Support non-prefixed ports

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This commit is contained in:
Edward Wang
2017-07-31 17:03:21 -07:00
committed by edwardcwang
parent a0e817b6fb
commit 513da4eb37
1 changed files with 1 additions and 1 deletions
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2
macros/src/test/scala/MacroCompilerSpec.scala
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@@ -119,7 +119,7 @@ trait HasSRAMGenerator {
write: Boolean, write: Boolean,
writeEnable: Boolean = false writeEnable: Boolean = false
): MacroPort = { ): MacroPort = {
val realPrefix = prefix + "_" val realPrefix = if (prefix == "") "" else prefix + "_"
MacroPort( MacroPort(
address=PolarizedPort(name=realPrefix + "addr", polarity=ActiveHigh), address=PolarizedPort(name=realPrefix + "addr", polarity=ActiveHigh),