diff --git a/macros/src/test/scala/MacroCompilerSpec.scala b/macros/src/test/scala/MacroCompilerSpec.scala
index 892e63d0..95547a20 100644
--- a/macros/src/test/scala/MacroCompilerSpec.scala
+++ b/macros/src/test/scala/MacroCompilerSpec.scala
@@ -119,7 +119,7 @@ trait HasSRAMGenerator {
     write: Boolean,
     writeEnable: Boolean = false
   ): MacroPort = {
-    val realPrefix = prefix + "_"
+    val realPrefix = if (prefix == "") "" else prefix + "_"
 
     MacroPort(
       address=PolarizedPort(name=realPrefix + "addr", polarity=ActiveHigh),