From 513da4eb37011c381f4e979bb9d97978e87df90e Mon Sep 17 00:00:00 2001
From: Edward Wang <edward.c.wang@compdigitec.com>
Date: Mon, 31 Jul 2017 17:03:21 -0700
Subject: [PATCH] Support non-prefixed ports

---
 macros/src/test/scala/MacroCompilerSpec.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/macros/src/test/scala/MacroCompilerSpec.scala b/macros/src/test/scala/MacroCompilerSpec.scala
index 892e63d0..95547a20 100644
--- a/macros/src/test/scala/MacroCompilerSpec.scala
+++ b/macros/src/test/scala/MacroCompilerSpec.scala
@@ -119,7 +119,7 @@ trait HasSRAMGenerator {
     write: Boolean,
     writeEnable: Boolean = false
   ): MacroPort = {
-    val realPrefix = prefix + "_"
+    val realPrefix = if (prefix == "") "" else prefix + "_"
 
     MacroPort(
       address=PolarizedPort(name=realPrefix + "addr", polarity=ActiveHigh),