5034d8d14b
Since operand and commit throughput are the same (2 cycles), it is unnecessary to stall the dpu during the multi-cycle commit. This enables the dpu to operate at full throughput of 1 operand every 2 cycles.
57 lines
1.3 KiB
Systemverilog
57 lines
1.3 KiB
Systemverilog
`ifdef EXT_T_ENABLE
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`include "VX_fpu_define.vh"
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module VX_tensor_dpu #(
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parameter ISW,
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parameter OCTET
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) (
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input clk,
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input reset,
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input stall,
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input valid_in,
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output ready_in,
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input [3:0][1:0][31:0] A_tile,
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input [1:0][3:0][31:0] B_tile,
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input [3:0][3:0][31:0] C_tile,
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output valid_out,
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output [3:0][3:0][31:0] D_tile
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);
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logic [3:0][3:0][31:0] result_hmma;
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always @(*) begin
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dpi_hmma(valid_in, A_tile, B_tile, C_tile, result_hmma);
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end
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logic ready_reg;
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always @(posedge clk) begin
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if (reset) begin
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ready_reg <= '1;
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end else if (valid_in) begin
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ready_reg <= '0;
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dpi_print_results(int'(ISW), int'(OCTET), A_tile, B_tile, C_tile, result_hmma);
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end else if (valid_out) begin
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ready_reg <= '1;
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end
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end
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// ready as soon as valid_out
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assign ready_in = ready_reg || valid_out;
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// fixed-latency model
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VX_shift_register #(
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.DATAW (1 + $bits(D_tile)),
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.DEPTH (`LATENCY_HMMA),
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.RESETW (1)
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) shift_reg (
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.clk (clk),
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.reset (reset),
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.enable (~stall),
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.data_in ({valid_in, result_hmma}),
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.data_out ({valid_out, D_tile})
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);
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endmodule
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`endif
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