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5034d8d14b548fd42bf983666ac1ad0d1d00c091
vortex/hw/rtl/fpu
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Hansung Kim 5034d8d14b tensor: Add buffer to hide 2cyc commit latency 
Since operand and commit throughput are the same (2 cycles), it is
unnecessary to stall the dpu during the multi-cycle commit.
This enables the dpu to operate at full throughput of 1 operand every 2
cycles.
2024-05-16 20:09:08 -07:00
..
VX_fpu_class.sv
Vortex 2.0 changes:
2023-11-10 02:47:05 -08:00
VX_fpu_cvt.sv
profiling update
2023-12-18 04:43:44 -08:00
VX_fpu_define.vh
synthesizable design
2024-04-17 18:05:51 -07:00
VX_fpu_div.sv
Vortex 2.0 changes:
2023-11-10 02:47:05 -08:00
VX_fpu_dpi.sv
Change result type for dpi calls from wire -> reg
2023-11-15 19:26:12 -08:00
VX_fpu_dsp.sv
Vortex 2.0 changes:
2023-11-10 02:47:05 -08:00
VX_fpu_fma.sv
Vortex 2.0 changes:
2023-11-10 02:47:05 -08:00
VX_fpu_fpnew.sv
firesim modifications
2024-05-07 13:59:25 -07:00
VX_fpu_ncomp.sv
Vortex 2.0 changes:
2023-11-10 02:47:05 -08:00
VX_fpu_pkg.sv
Vortex 2.0 changes:
2023-11-10 02:47:05 -08:00
VX_fpu_rounding.sv
minor update
2023-11-12 23:40:59 -08:00
VX_fpu_sqrt.sv
Vortex 2.0 changes:
2023-11-10 02:47:05 -08:00
VX_fpu_to_csr_if.sv
Vortex 2.0 changes:
2023-11-10 02:47:05 -08:00
VX_tensor_dpu.sv
tensor: Add buffer to hide 2cyc commit latency
2024-05-16 20:09:08 -07:00
VX_tensor_tb.sv
initial tcore impl
2024-03-21 01:29:38 -07:00