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5034d8d14b548fd42bf983666ac1ad0d1d00c091
vortex/hw/rtl
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Hansung Kim 5034d8d14b tensor: Add buffer to hide 2cyc commit latency 
Since operand and commit throughput are the same (2 cycles), it is
unnecessary to stall the dpu during the multi-cycle commit.
This enables the dpu to operate at full throughput of 1 operand every 2
cycles.
2024-05-16 20:09:08 -07:00
..
afu
minor update
2023-11-12 23:40:59 -08:00
cache
synthesizable design
2024-04-17 18:05:51 -07:00
core
tensor: Add buffer to hide 2cyc commit latency
2024-05-16 20:09:08 -07:00
fpu
tensor: Add buffer to hide 2cyc commit latency
2024-05-16 20:09:08 -07:00
interfaces
Add perf counter for stall by any operand hazard
2024-04-15 01:01:26 -07:00
libs
proper srams
2024-05-07 13:52:07 -07:00
mem
synthesizable design
2024-04-17 18:05:51 -07:00
.DS_Store
project directories reorganization
2020-04-14 06:35:20 -04:00
Vortex_axi.sv
Vortex 2.0 changes:
2023-11-10 02:47:05 -08:00
Vortex.sv
adding tracking for SFU stalls
2023-12-28 12:12:11 -08:00
VX_cluster.sv
minor updates
2023-12-30 00:52:44 -08:00
VX_config.vh
tensor: Add buffer to hide 2cyc commit latency
2024-05-16 20:09:08 -07:00
VX_core_wrapper.sv
store fencing, large smem, fix tensor core for firesim
2024-05-15 21:45:48 -07:00
VX_define.vh
initial tensor core
2024-03-20 02:46:00 -07:00
VX_gpu_pkg.sv
minor updates
2023-12-30 00:52:44 -08:00
VX_platform.vh
store fencing, large smem, fix tensor core for firesim
2024-05-15 21:45:48 -07:00
VX_scope.vh
Vortex 2.0 changes:
2023-11-10 02:47:05 -08:00
VX_socket.sv
minor updates
2023-12-30 00:52:44 -08:00
VX_types.vh
accelerator cisc
2024-05-07 13:58:32 -07:00