61 lines
1.8 KiB
Verilog
61 lines
1.8 KiB
Verilog
`include "VX_platform.vh"
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module VX_rr_arbiter #(
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parameter NUM_REQS = 1,
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parameter LOCK_ENABLE = 0,
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parameter LOG_NUM_REQS = $clog2(NUM_REQS)
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) (
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input wire clk,
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input wire reset,
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input wire enable,
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input wire [NUM_REQS-1:0] requests,
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output wire [LOG_NUM_REQS-1:0] grant_index,
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output wire [NUM_REQS-1:0] grant_onehot,
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output wire grant_valid
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);
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if (NUM_REQS == 1) begin
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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assign grant_index = 0;
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assign grant_onehot = requests;
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assign grant_valid = requests[0];
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end else begin
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reg [LOG_NUM_REQS-1:0] grant_table [NUM_REQS-1:0];
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reg [LOG_NUM_REQS-1:0] state;
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always @(*) begin
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for (integer i = 0; i < NUM_REQS; i++) begin
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grant_table[i] = LOG_NUM_REQS'(i);
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for (integer j = 0; j < NUM_REQS; j++) begin
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if (requests[(i+j) % NUM_REQS]) begin
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grant_table[i] = LOG_NUM_REQS'((i+j) % NUM_REQS);
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end
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end
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end
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end
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always @(posedge clk) begin
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if (reset) begin
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state <= 0;
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end else if (!LOCK_ENABLE || enable) begin
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state <= grant_table[state];
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end
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end
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reg [NUM_REQS-1:0] grant_onehot_r;
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always @(*) begin
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grant_onehot_r = NUM_REQS'(0);
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grant_onehot_r[grant_table[state]] = 1;
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end
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assign grant_index = grant_table[state];
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assign grant_onehot = grant_onehot_r;
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assign grant_valid = (| requests);
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end
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endmodule |