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29cd2f5dffad583751853087a4e34dba72b0c1ba
vortex/hw/rtl
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Blaise Tine 29cd2f5dff fixed register file initialization to zero synthesis inference
2020-12-10 00:27:56 -08:00
..
afu
adding missing files, buffering teh snoop forwarder
2020-12-09 00:24:32 -08:00
cache
minor update
2020-12-09 00:57:31 -08:00
fp_cores
minor update
2020-12-09 05:34:27 -08:00
interfaces
minor update
2020-12-09 05:49:02 -08:00
libs
fixed typo
2020-12-09 13:03:22 -08:00
tex_unit
modelsim fixes && pipeline optimization
2020-07-28 14:20:23 -07:00
.DS_Store
project directories reorganization
2020-04-14 06:35:20 -04:00
.gitignore
fix opae build
2020-04-20 12:51:42 -07:00
Vortex.v
adding missing files, buffering teh snoop forwarder
2020-12-09 00:24:32 -08:00
VX_alu_unit.v
register file refactoring
2020-12-05 01:40:50 -08:00
VX_cluster.v
adding missing files, buffering teh snoop forwarder
2020-12-09 00:24:32 -08:00
VX_commit.v
register file refactoring
2020-12-05 01:40:50 -08:00
VX_config.vh
merging perf counters
2020-12-08 21:02:39 -08:00
VX_core.v
merging perf counters
2020-12-08 21:02:39 -08:00
VX_csr_arb.v
CSR IO's critical path elimination
2020-12-06 16:07:36 -08:00
VX_csr_data.v
minor update
2020-12-09 05:49:02 -08:00
VX_csr_io_arb.v
cache req datapath optimizations
2020-12-08 02:58:08 -08:00
VX_csr_unit.v
fixed register file initialization to zero synthesis inference
2020-12-10 00:27:56 -08:00
VX_databus_arb.v
cache req datapath optimizations
2020-12-08 02:58:08 -08:00
VX_dcache_arb.v
minor update
2020-12-09 05:34:27 -08:00
VX_decode.v
register file refactoring
2020-12-05 01:40:50 -08:00
VX_define.vh
merging perf counters
2020-12-08 21:02:39 -08:00
VX_execute.v
merging perf counters
2020-12-08 21:02:39 -08:00
VX_fetch.v
scope fixes
2020-10-13 08:44:55 -07:00
VX_fpu_unit.v
register file refactoring
2020-12-05 01:40:50 -08:00
VX_gpr_ram_f.v
fixed register file initialization to zero synthesis inference
2020-12-10 00:27:56 -08:00
VX_gpr_ram_i.v
fixed register file initialization to zero synthesis inference
2020-12-10 00:27:56 -08:00
VX_gpr_stage.v
fixed register file initialization to zero synthesis inference
2020-12-10 00:27:56 -08:00
VX_gpu_unit.v
register file refactoring
2020-12-05 01:40:50 -08:00
VX_ibuffer.v
register file refactoring
2020-12-05 01:40:50 -08:00
VX_icache_stage.v
RAM blocks inference fixes
2020-11-30 14:02:47 -08:00
VX_instr_demux.v
fixed typo
2020-12-09 13:03:22 -08:00
VX_ipdom_stack.v
RAM blocks inference fixes
2020-11-30 14:02:47 -08:00
VX_issue.v
merging perf counters
2020-12-08 21:02:39 -08:00
VX_lsu_unit.v
register file refactoring
2020-12-05 01:40:50 -08:00
VX_mem_arb.v
cache req datapath optimizations
2020-12-08 02:58:08 -08:00
VX_mem_unit.v
minor update
2020-12-09 05:49:02 -08:00
VX_mul_unit.v
register file refactoring
2020-12-05 01:40:50 -08:00
VX_pipeline.v
merging perf counters
2020-12-08 21:02:39 -08:00
VX_platform.vh
fixed DRAM response backpressure inside Cache
2020-11-10 05:24:57 -08:00
VX_print_instr.vh
optimize warp_sched
2020-08-24 05:36:00 -07:00
VX_scope.vh
cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count
2020-11-02 01:50:12 -08:00
VX_scoreboard.v
register file refactoring
2020-12-05 01:40:50 -08:00
VX_types.vh
fixed register file initialization to zero synthesis inference
2020-12-10 00:27:56 -08:00
VX_warp_sched.v
register file refactoring
2020-12-05 01:40:50 -08:00
VX_writeback.v
register file refactoring
2020-12-05 01:40:50 -08:00