Support 4-lane Blackwell tensor wrapper

hw/rtl/core/VX_tensor_blackwell_core.sv

@@ -28,6 +28,9 @@ module VX_tensor_blackwell_core_block import VX_gpu_pkg::*; #(
     VX_tc_bus_if.master smem_B_if,
     VX_commit_if.master commit_if
 );
+    `STATIC_ASSERT((`NUM_THREADS == 4),
+        ("4-lane Blackwell tensor core wrapper requires NUM_THREADS == 4"))
+
     localparam NUM_LANES = `NUM_THREADS;
     localparam METADATA_QUEUE_DEPTH = 2;
 
@@ -144,10 +147,6 @@ module VX_tensor_blackwell_core_block import VX_gpu_pkg::*; #(
         .io_writeback_bits_data_1(writeback_data[1]),
         .io_writeback_bits_data_2(writeback_data[2]),
         .io_writeback_bits_data_3(writeback_data[3]),
-        .io_writeback_bits_data_4(writeback_data[4]),
-        .io_writeback_bits_data_5(writeback_data[5]),
-        .io_writeback_bits_data_6(writeback_data[6]),
-        .io_writeback_bits_data_7(writeback_data[7]),
 
         .io_respA_ready(tmem_if.rsp_ready),
         .io_respA_valid(tmem_if.rsp_valid),

hw/rtl/core/VX_tensor_ctrl_unit.sv

@@ -91,7 +91,7 @@ module VX_tensor_ctrl_unit import VX_gpu_pkg::*; #(
     assign barrier.id = req_rs1_data[`NB_WIDTH-1:0];
 `ifdef GBAR_ENABLE
 `ifdef GBAR_CLUSTER_ENABLE
-    assign barrier.is_global = 1'b1;
+    assign barrier.is_global = is_bar_mask ? 1'b0 : 1'b1;
 `else
     assign barrier.is_global = req_rs1_data[31];
 `endif

hw/rtl/core/VX_wctl_unit.sv

@@ -113,9 +113,9 @@ module VX_wctl_unit import VX_gpu_pkg::*; #(
     assign barrier.id       = rs1_data[`NB_WIDTH-1:0];
 `ifdef GBAR_ENABLE
 `ifdef GBAR_CLUSTER_ENABLE
-    // all barriers are cluster-wide barriers, which is implemented by
-    // modifying the global barrier logic
-    assign barrier.is_global = 1'b1;
+    // Explicit warp masks are core-local; rs2 carries the mask, not a warp
+    // count for the cluster global-barrier protocol.
+    assign barrier.is_global = is_bar_mask ? 1'b0 : 1'b1;
 `else
     assign barrier.is_global = rs1_data[31];
 `endif