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merge into: wu-arch:wu-architecture
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wu-arch:wu-architecture wu-arch:wu-blackwell-4lane-tc wu-arch:master
...
pull from: wu-arch:wu-blackwell-4lane-tc
Branches Tags
wu-arch:wu-blackwell-4lane-tc wu-arch:wu-architecture wu-arch:master

1 Commits
wu-archite ... wu-blackwe

Author SHA1 Message Date
Zhongdi LUO
abee301b6e Support 4-lane Blackwell tensor wrapper 2026-05-27 05:54:24 +00:00
1 changed files with 3 additions and 4 deletions
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7
hw/rtl/core/VX_tensor_blackwell_core.sv
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@@ -28,6 +28,9 @@ module VX_tensor_blackwell_core_block import VX_gpu_pkg::*; #(
VX_tc_bus_if.master smem_B_if,
VX_commit_if.master commit_if
);
`STATIC_ASSERT((`NUM_THREADS == 4),
("4-lane Blackwell tensor core wrapper requires NUM_THREADS == 4"))
localparam NUM_LANES = `NUM_THREADS;
localparam METADATA_QUEUE_DEPTH = 2;
@@ -144,10 +147,6 @@ module VX_tensor_blackwell_core_block import VX_gpu_pkg::*; #(
.io_writeback_bits_data_1(writeback_data[1]),
.io_writeback_bits_data_2(writeback_data[2]),
.io_writeback_bits_data_3(writeback_data[3]),
.io_writeback_bits_data_4(writeback_data[4]),
.io_writeback_bits_data_5(writeback_data[5]),
.io_writeback_bits_data_6(writeback_data[6]),
.io_writeback_bits_data_7(writeback_data[7]),
.io_respA_ready(tmem_if.rsp_ready),
.io_respA_valid(tmem_if.rsp_valid),